參數(shù)資料
型號(hào)： PIC16CR77T-I/ML
廠商： Microchip Technology
文件頁數(shù)： 38/172頁
文件大小： 0K
描述： IC PIC MCU 8KX14 44QFN
標(biāo)準(zhǔn)包裝： 1,600
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 33
程序存儲(chǔ)器容量： 14KB（8K x 14）
程序存儲(chǔ)器類型： ROM
RAM 容量： 368 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤
包裝： 帶卷 (TR)
PIC18F2220/2320/4220/4320
DS39599G-page 130
2007 Microchip Technology Inc.
14.1
Timer3 Operation
Timer3 can operate in one of these modes:
As a timer
As a synchronous counter
As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).
When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC1:TRISC0 value
is ignored and the pins are read as ‘0’.
Timer3 also has an internal “Reset input”. This Reset
can be generated by the CCP module (see
FIGURE 14-1:
TIMER3 BLOCK DIAGRAM
FIGURE 14-2:
TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE
TMR3H
TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
TMR3IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
Flag bit
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
T1CKI
CLR
CCP Special Event Trigger
T3CCPx
Timer3
TMR3L
T1OSC
T3SYNC
TMR3CS
T3CKPS1:T3CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
Clock
TMR3ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
1
Synchronized
Clock Input
2
T1OSO/
T1OSI
TMR3
T1CKI
CLR
CCP Special Event Trigger
T3CCPx
To Timer1 Clock Input
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR3H
8
Read TMR3L
Write TMR3L
Set TMR3IF Flag bit
on Overflow
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