參數(shù)資料
型號: PIC16CR77-I/ML
廠商: Microchip Technology
文件頁數(shù): 105/172頁
文件大?。?/td> 0K
描述: IC PIC MCU 8KX14 44QFN
標(biāo)準(zhǔn)包裝: 45
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: ROM
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
PIC16CR7X
DS21993C-page 36
2007 Microchip Technology Inc.
4.4
PORTD and TRISD Registers
This section is not applicable to the PIC16CR73 or
PIC16CR76.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configureable as an input or
output.
PORTD can be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL.
FIGURE 4-6:
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
TABLE 4-7:
PORTD FUNCTIONS
TABLE 4-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Data Bus
WR Port
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Q
D
CK
Q
D
CK
EN
QD
EN
Name
Bit#
Buffer Type
Function
RD0/PSP0
bit 0
ST/TTL(1)
Input/output port pin or parallel slave port bit 0
RD1/PSP1
bit 1
ST/TTL(1)
Input/output port pin or parallel slave port bit 1
RD2/PSP2
bit 2
ST/TTL(1)
Input/output port pin or parallel slave port bit 2
RD3/PSP3
bit 3
ST/TTL(1)
Input/output port pin or parallel slave port bit 3
RD4/PSP4
bit 4
ST/TTL(1)
Input/output port pin or parallel slave port bit 4
RD5/PSP5
bit 5
ST/TTL(1)
Input/output port pin or parallel slave port bit 5
RD6/PSP6
bit 6
ST/TTL(1)
Input/output port pin or parallel slave port bit 6
RD7/PSP7
bit 7
ST/TTL(1)
Input/output port pin or parallel slave port bit
Legend:
ST = Schmitt Trigger input, TTL = TTL input
Note 1:
Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
08h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
88h
TRISD
PORTD Data Direction Register
1111 1111
89h
TRISE
IBF
OBF
IBOV
PSPMODE
PORTE Data Direction bits
0000 -111
Legend:
x
= unknown, u = unchanged, – = unimplemented read as ‘0’. Shaded cells are not used by PORTD.
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