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鍙冩暩璩囨枡
| 鍨嬭櫉锛� | PIC16CR73-I/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩锛� | 78/172闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC PIC MCU 4KX14 28SSOP |
| 妯欐簴鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁革細 | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 7KB锛�4K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROM |
| RAM 瀹归噺锛� | 192 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 2 V ~ 5.5 V |
| 鏁告摎杞夋彌鍣細 | A/D 5x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏ч儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
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2007 Microchip Technology Inc.
DS39599G-page 167
PIC18F2220/2320/4220/4320
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE)
R/W-0
GCEN
ACKSTAT
ACKDT(1)
ACKEN
RCEN
PEN
RSEN
SEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 鈥�0鈥�
-n = Value at POR
鈥�1鈥� = Bit is set
鈥�0鈥� = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)(1)
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically
cleared by hardware.
0 = Acknowledge sequence Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I2C
0 = Receive Idle
bit 2
PEN: Stop Condition Enable bit (Master mode only)
1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Stop condition Idle
bit 1
RSEN: Repeated Start Condition Enabled bit (Master mode only)
1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
bit 0
SEN: Start Condition Enabled/Stretch Enabled bit
In Master mode:
1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)
0 = Clock stretching is disabled
Note 1:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
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鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁� |
鍙冩暩鎻忚堪 |
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