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| 型號： | PIC16CE625T-30/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 19/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 2KX14 EE COMP 18SOIC |
| 標準包裝： | 1,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 30MHz |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16CE625T30/SO |
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1999 Microchip Technology Inc.
DS40182C-page 15
PIC16CE62X
4.2.2.1
STATUS REGISTER
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the status register as
000uu1uu
(where u = unchanged).
It is recommended, therefore, that only BCF,
BSF,
SWAPF
and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
Note 1:
The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16CE62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits
is NOT recommended, since this may
affect upward compatibility with future
products.
Note 2:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved
R/W-0
R-1
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit7
bit0
bit 7:
IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5
RP<1:O>: Register Bank Select bits (used for direct addressing)
11
= Bank 3 (180h - 1FFh)
10
= Bank 2 (100h - 17Fh)
01
= Bank 1 (80h - FFh)
00
= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4:
TO: Time-out bit
1
= After power-up, CLRWDT instruction, or SLEEP instruction
0
= A WDT time-out occurred
bit 3:
PD: Power-down bit
1
= After power-up or by the CLRWDT instruction
0
= By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1
= A carry-out from the 4th low order bit of the result occurred
0
= No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1
= A carry-out from the most significant bit of the result occurred
0
= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
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