參數(shù)資料
型號(hào): PIC16C925T-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 13/24頁(yè)
文件大小: 0K
描述: IC MCU OTP 4KX14 LCD DVR 64TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲(chǔ)器容量: 7KB(4K x 14)
程序存儲(chǔ)器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
配用: DVA16PQ640-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164023-ND - MODULE SKT PROMATEII 68TQFP
其它名稱: PIC16C925TI/PT
CS61584A
48
DS261PP5
13. APPLICATIONS
13.1
Line Interface
Figures 27-29 illustrate typical connection diagram
for T1 and E1 line interface circuits in Hardware,
Host serial port, and Host parallel port modes. Ta-
ble 13 lists the external components that are re-
quired in T1 and E1 applications for both the 5.0
and 3.3 Volt devices.
In the transmit line interface circuitry, capacitors
C1 and C2 provide transmitter return loss. The
0.47 F capacitor in series with the transformer pri-
mary prevents output stage imbalances from pro-
ducing a DC current through the transformer that
might saturate the transformer and result in an out-
put level offset.
In the receive line interface circuitry, resistors R1-
R4 provide receive impedance matching and re-
ceiver return loss. The 0.47 F capacitor to ground
provides the necessary differential input voltage
reference for the receiver.
Device Suffix
Data Rate
(MHz)
REFCLK Frequency (MHz)
Transformer
Turns Ratio
Cable
(
)
R1-R4
(
)
C1-C2
(pF)
1XCLK = 1
1XCLK = 0
-IL3 and -IQ3 (3.3 Volts)
1.544
12.352
1:2
100
12.4
560
2.048
16.384
75
9.31
2200
120
15.0
560
-IL5 and -IQ5 (5.0 Volts)
1.544
12.352
1:1.15
100
38.3
220
2.048
16.384
75
28.7
470
120
45.3
220
Table 13. CS61584A External Components
AV+
AGND
BGREF
TV+1
TGND1
RV+1
RGND1 DV+ DGND1:3
0.01
F
TCLK1
TPOS1
TNEG1
RCLK1
RPOS1
RNEG1
TCLK2
TPOS2
TNEG2
RCLK2
RPOS2
RNEG2
Framer
TTIP1
TRING1
RTIP1
RRING1
TTIP2
TRING2
RTIP2
RRING2
Hardware Control
Power Supply
Clock Generator
Channel 2
Channel 1
transmit
3
0.1
F
1
F
+
0.1
F
TV+2
TGND2
RV+2
RGND2
22
F
+
0.1
F
0.1
F
0.1
F
receive
R3
R4
receive
R1
R2
T1
T2
T3
T4
R3
4.99k
VCC
0.47
F
0.47
F
REFCLK 1XCLK
RESET
CLKE
TAOS[1:2]
RLOOP[1:2] LLOOP
CON[0:2]1 CON[0:2]2
ATTEN[0:1]
C1
C2
0.47
F
0.47
F
LOS[1:2]
PD[1:2]
MODE
2
3
22
3
2
1:N
Figure 27. Hardware Mode Configuration
CS61584A
48
DS261F1
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