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參數(shù)資料
| 型號(hào)： | PIC16C773-20I/SS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO28 |
| 封裝： | 5.30 MM, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 38/201頁 |
| 文件大?。?/td> | 2669K |
| 代理商： | PIC16C773-20I/SS |
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PIC16C77X
DS30275A-page 132
Advance Information
1999 Microchip Technology Inc.
12.4
Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details. For
a slow rise time, see Figure 12-6.
Two delay timers have been provided which hold the
device in reset after a POR (dependant upon device
configuration) so that all operational parameters have
been met prior to releasing to device to resume/begin
normal operation.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the startup con-
ditions, or if necessary an external POR circuit may be
implemented to delay end of reset for as long as
needed.
FIGURE 12-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
12.5
Power-up Timer (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up type resets only. For a POR, the
PWRT is invoked when the POR pulse is generated.
For a BOR, the PWRT is invoked when the device exits
the reset condition (VDD rises above BOR trippoint).
The Power-up Timer operates on an internal RC oscil-
lator. The chip is kept in reset as long as the PWRT is
active. The PWRT’s time delay is designed to allow VDD
to rise to an acceptable level. A configuration bit is pro-
vided to enable/disable the PWRT for the POR only. For
a BOR the PWRT is always available regardless of the
configuration bit setting.
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on a power-up type reset or a wake-up
from SLEEP.
12.7
Brown-Out Reset (BOR)
The Brown-out Reset module is used to generate a
reset when the supply voltage falls below a specified
trip voltage. The trip voltage is configurable to any one
of four voltages provided by the BORV1:BORV0 config-
uration word bits.
Configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below the specified trippoint for
greater than parameter #35 in the electrical specifica-
tions section, the brown-out situation will reset the chip.
A reset may not occur if VDD falls below the trippoint for
less than parameter #35. The chip will remain in Brown-
out Reset until VDD rises above BVDD. The Power-up
Timer will be invoked at that point and will keep the chip
in RESET an additional 72 ms. If VDD drops below
BVDD while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up
Timer will be re-initialized. Once VDD rises above
BVDD, the Power-up Timer will again begin a 72 ms
time delay. Even though the PWRT is always enabled
when brown-out is enabled, the PWRT configuration
word bit should be cleared (enabled) when brown-out is
enabled.
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 k
is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100
to 1 k will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
C
R1
R
D
VDD
MCLR
PIC16C77X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16C773-E/SO | 功能描述:8位微控制器 -MCU 7KB 256 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C773-E/SP | 功能描述:8位微控制器 -MCU 7KB 256 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C773-E/SS | 功能描述:8位微控制器 -MCU 7KB 256 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C773-I/SO | 功能描述:8位微控制器 -MCU 7KB 256 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C773-I/SO | 制造商:Microchip Technology Inc 功能描述:8BIT CMOS MCU SMD 16C773 SOIC28 |
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