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  • 參數(shù)資料
    型號: PIC16C77-10/L
    廠商: Microchip Technology
    文件頁數(shù): 31/114頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 8KX14 A/D PWM 44PLCC
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 27
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 10MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
    輸入/輸出數(shù): 33
    程序存儲器容量: 14KB(8K x 14)
    程序存儲器類型: OTP
    RAM 容量: 368 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 44-LCC(J 形引線)
    包裝: 管件
    配用: AC164309-ND - MODULE SKT FOR PM3 44PLCC
    444-1001-ND - DEMO BOARD FOR PICMICRO MCU
    309-1040-ND - ADAPTER 44-PLCC ZIF TO 40-DIP
    309-1039-ND - ADAPTER 44-PLCC TO 40-DIP
    1997 Microchip Technology Inc.
    DS30390E-page 23
    PIC16C7X
    4.2.2
    SPECIAL FUNCTION REGISTERS
    The Special Function Registers are registers used by
    the CPU and Peripheral Modules for controlling the
    desired operation of the device. These registers are
    implemented as static RAM.
    The special function registers can be classied into two
    sets (core and peripheral). Those registers associated
    with the “core” functions are described in this section,
    and those related to the operation of the peripheral fea-
    tures are described in the section of that peripheral fea-
    ture.
    TABLE 4-1:
    PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY
    Address Name
    Bit 7
    Bit 6
    Bit 5
    Bit 4
    Bit 3
    Bit 2
    Bit 1
    Bit 0
    Value on:
    POR,
    BOR
    Value on all
    other resets
    (3)
    Bank 0
    00h(1)
    INDF
    Addressing this location uses contents of FSR to address data memory (not a physical register)
    0000 0000
    01h
    TMR0
    Timer0 module’s register
    xxxx xxxx
    uuuu uuuu
    02h(1)
    PCL
    Program Counter's (PC) Least Signicant Byte
    0000 0000
    03h(1)
    STATUS
    IRP(4)
    RP1(4)
    RP0
    TO
    PD
    ZDC
    C
    0001 1xxx
    000q quuu
    04h(1)
    FSR
    Indirect data memory address pointer
    xxxx xxxx
    uuuu uuuu
    05h
    PORTA
    PORTA Data Latch when written: PORTA pins when read
    --0x 0000
    --0u 0000
    06h
    PORTB
    PORTB Data Latch when written: PORTB pins when read
    xxxx xxxx
    uuuu uuuu
    07h
    PORTC
    PORTC Data Latch when written: PORTC pins when read
    xxxx xxxx
    uuuu uuuu
    08h
    Unimplemented
    09h
    Unimplemented
    0Ah(1,2)
    PCLATH
    Write Buffer for the upper 5 bits of the Program Counter
    ---0 0000
    0Bh(1)
    INTCON
    GIE
    PEIE
    T0IE
    INTE
    RBIE
    T0IF
    INTF
    RBIF
    0000 000x
    0000 000u
    0Ch
    PIR1
    ADIF
    SSPIF
    CCP1IF
    TMR2IF
    TMR1IF
    -0-- 0000
    0Dh
    Unimplemented
    0Eh
    TMR1L
    Holding register for the Least Signicant Byte of the 16-bit TMR1 register
    xxxx xxxx
    uuuu uuuu
    0Fh
    TMR1H
    Holding register for the Most Signicant Byte of the 16-bit TMR1 register
    xxxx xxxx
    uuuu uuuu
    10h
    T1CON
    T1CKPS1
    T1CKPS0
    T1OSCEN
    T1SYNC
    TMR1CS
    TMR1ON
    --00 0000
    --uu uuuu
    11h
    TMR2
    Timer2 module’s register
    0000 0000
    12h
    T2CON
    TOUTPS3
    TOUTPS2
    TOUTPS1
    TOUTPS0
    TMR2ON
    T2CKPS1
    T2CKPS0
    -000 0000
    13h
    SSPBUF
    Synchronous Serial Port Receive Buffer/Transmit Register
    xxxx xxxx
    uuuu uuuu
    14h
    SSPCON
    WCOL
    SSPOV
    SSPEN
    CKP
    SSPM3
    SSPM2
    SSPM1
    SSPM0
    0000 0000
    15h
    CCPR1L
    Capture/Compare/PWM Register (LSB)
    xxxx xxxx
    uuuu uuuu
    16h
    CCPR1H
    Capture/Compare/PWM Register (MSB)
    xxxx xxxx
    uuuu uuuu
    17h
    CCP1CON
    CCP1X
    CCP1Y
    CCP1M3
    CCP1M2
    CCP1M1
    CCP1M0
    --00 0000
    18h
    Unimplemented
    19h
    Unimplemented
    1Ah
    Unimplemented
    1Bh
    Unimplemented
    1Ch
    Unimplemented
    1Dh
    Unimplemented
    1Eh
    ADRES
    A/D Result Register
    xxxx xxxx
    uuuu uuuu
    1Fh
    ADCON0
    ADCS1
    ADCS0
    CHS2
    CHS1
    CHS0
    GO/DONE
    ADON
    0000 00-0
    Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
    Shaded locations are unimplemented, read as ‘0’.
    Note 1:
    These registers can be addressed from either bank.
    2:
    The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
    contents are transferred to the upper byte of the program counter.
    3:
    Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
    4:
    The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
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