參數資料
型號: PIC16C765-I/PT
廠商: Microchip Technology
文件頁數: 101/165頁
文件大?。?/td> 0K
描述: IC MCU OTP 8KX14 USB 44TQFP
產品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 24MHz
連通性: SCI,UART/USART,USB
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數: 33
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: OTP
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.35 V ~ 5.25 V
數據轉換器: A/D 8x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
產品目錄頁面: 636 (CN2011-ZH PDF)
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
PIC16C745/765
DS41124C-page 40
Preliminary
2000 Microchip Technology Inc.
5.6
Parallel Slave Port (PSP)
PORTD operates as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port when control bit PSP-
MODE (TRISE<4>) is set. In slave mode, it is asyn-
chronously readable and writable by the external world
through RD control input pin RE0/RD/AN5 and WR
control input pin RE1/WR/AN6.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input, RE1/
WR/AN6 to be the WR input and RE2/CS/AN7 to be
the CS (chip select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the
A/D
port
configuration
bits
PCFG<2:0>
(ADCON1<2:0>) must be set, which will configure pins
RE<2:0> as digital I/O.
There are actually two 8-bit latches; one for data-out
(from the PICmicro microcontroller) and one for data
input. The user writes 8-bit data to PORTD data latch
and reads data from the port pin latch (note that they
have the same address). In this mode, the TRISD reg-
ister is ignored, since the microprocessor is controlling
the direction of data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full (IBF) status flag bit (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-9). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The Input Buffer Overflow (IBOV) status
flag bit (TRISE<5>) is set if a second write to the PSP
is attempted when the previous byte has not been read
out of the buffer.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 5-10) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
FIGURE 5-8:
PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
Note:
The PIC16C745 does not provide a paral-
lel slave port. The PORTD, PORTE, TRISD
and TRISE registers are reserved. Always
maintain these bits clear.
Data Bus
WR
Port
RD
RDx
Q
D
CK
EN
QD
EN
Port
pin
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Read
Chip Select
Write
RD
CS
WR
TTL
VDD
745cov.book Page 40 Wednesday, August 2, 2000 8:24 AM
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