參數(shù)資料
型號: PIC16C745/JW
廠商: Microchip Technology
文件頁數(shù): 105/165頁
文件大?。?/td> 0K
描述: IC MCU EPROM8KX14 USB A/D 28CDIP
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 24MHz
連通性: SCI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: EPROM,UV
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 4.35 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x8b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 28-CDIP(0.300",7.62mm)窗口
包裝: 管件
PIC16C745/765
DS41124C-page 44
Preliminary
2000 Microchip Technology Inc.
6.2
Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
6.3
Prescaler
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
module means that there is no prescaler for the watch-
dog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 6-1).
The PSA and PS<2:0> bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x
....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the watchdog timer. The prescaler is not
readable or writable.
To avoid an unintended device RESET, the following
instruction sequence (shown in Example 6-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
EXAMPLE 6-1:
CHANGING PRESCALER (TIMER0
→WDT)
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Note:
Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
1)
BSF
STATUS, RP0
;Bank1
Lines 2 and 3 do
NOT have to be
included if the final
desired prescale
value is other than
1:1. If 1:1 is the final
desired value, then a
temporary prescale
value is set in lines 2
and 3 and the final
prescale value will
be set in lines 10
and 11.
2)
MOVLW
b’xx0x0xxx’
;Select clock source and prescale value of
3)
MOVWF
OPTION_REG
;other than 1:1
4)
BCF
STATUS, RP0
;Bank0
5)
CLRF
TMR0
;Clear TMR0 and prescaler
6)
BSF
STATUS, RP1
;Bank1
7)
MOVLW
b’xxxx1xxx’
;Select WDT, do not change prescale value
8)
MOVWF
OPTION_REG
;
9)
CLRWDT
;Clears WDT and prescaler
10) MOVLW
b’xxxx1xxx’
;Select new prescale value and WDT
11) MOVWF
OPTION_REG
;
12) BCF
STATUS, RP0
;Bank0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
01h,101h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
81h,181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
745cov.book Page 44 Wednesday, August 2, 2000 8:24 AM
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