PIC16C745/765
DS41124C-page 24
Preliminary
2000 Microchip Technology Inc.
4.2.2.3
INTCON REGISTER
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
REGISTER 4-3:
INTERRUPT CONTROL REGISTER (INTCON: 10Bh, 18Bh)
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit7
bit0
bit 7:
GIE: Global Interrupt Enable bit
1
= Enables all un-masked interrupts
0
= Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1
= Enables all un-masked peripheral interrupts
0
= Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1
= Enables the TMR0 interrupt
0
= Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1
= Enables the RB0/INT external interrupt
0
= Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1
= Enables the RB port change interrupt
0
= Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1
= TMR0 register has overflowed (must be cleared in software)
0
= TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1
= The RB0/INT external interrupt occurred (must be cleared in software)
0
= The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1
= At least one of the RB<7:4> pins changed state (must be cleared in software)
0
= None of the RB<7:4> pins have changed state
745cov.book Page 24 Wednesday, August 2, 2000 8:24 AM
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