參數(shù)資料
型號： PIC16C745-I/SO
廠商： Microchip Technology
文件頁數(shù)： 104/165頁
文件大小： 0K
描述： IC MCU OTP 8KX14 USB A/D 28SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 27
系列： PIC® 16C
核心處理器： PIC
芯體尺寸： 8-位
速度： 24MHz
連通性： SCI，UART/USART，USB
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 14KB（8K x 14）
程序存儲器類型： OTP
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 4.35 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 5x8b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 636 (CN2011-ZH PDF)
配用： XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
2000 Microchip Technology Inc.
Preliminary
DS41124C-page 43
PIC16C745/765
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt-on-overflow from FFh to 00h
Edge select for external clock
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Additional information on the Timer0 module is avail-
able in the PICmicro Mid-Range MCU Family Refer-
ence Manual (DS33023).
Timer
mode is
selected by
clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the
Timer0
Source
Edge
Select
bit
T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The pres-
caler is not readable or writable. Section 6.3 details the
operation of the prescaler.
6.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP.
FIGURE 6-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
RA4/T0CKI
T0SE
Pin
M
U
X
FINT
SYNC
2
Cycles
TMR0 reg
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
0
1
0
1
WDT
Time-out
PS<2:0>
8
Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
1
0
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
TOCS
PRESCALER
745cov.book Page 43 Wednesday, August 2, 2000 8:24 AM
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