SSP I2C Operation " />
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    參數(shù)資料
    型號: PIC16C73AT-20I/SO
    廠商: Microchip Technology
    文件頁數(shù): 108/114頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 4KX14 A/D PWM 28SOIC
    標準包裝: 1,600
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 20MHz
    連通性: I²C,SPI,UART/USART
    外圍設備: 欠壓檢測/復位,POR,PWM,WDT
    輸入/輸出數(shù): 22
    程序存儲器容量: 7KB(4K x 14)
    程序存儲器類型: OTP
    RAM 容量: 192 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
    數(shù)據轉換器: A/D 5x8b
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
    包裝: 帶卷 (TR)
    1997 Microchip Technology Inc.
    DS30390E-page 93
    PIC16C7X
    11.5
    SSP I2C Operation
    The SSP module in I2C mode fully implements all slave
    functions, except general call support, and provides
    interrupts on start and stop bits in hardware to facilitate
    rmware implementations of the master functions. The
    SSP module implements the standard mode specica-
    tions as well as 7-bit and 10-bit addressing. Two pins
    are
    used
    for
    data
    transfer.
    These
    are
    the
    RC3/SCK/SCL pin, which is the clock (SCL), and the
    RC4/SDI/SDA pin, which is the data (SDA). The user
    must congure these pins as inputs or outputs through
    the TRISC<4:3> bits. The SSP module functions are
    enabled by setting SSP Enable bit SSPEN (SSP-
    CON<5>).
    FIGURE 11-24: SSP BLOCK DIAGRAM
    (I2C MODE)
    The SSP module has ve registers for I2C operation.
    These are the:
    SSP Control Register (SSPCON)
    SSP Status Register (SSPSTAT)
    Serial Receive/Transmit Buffer (SSPBUF)
    SSP Shift Register (SSPSR) - Not directly acces-
    sible
    SSP Address Register (SSPADD)
    Read
    Write
    SSPSR reg
    Match detect
    SSPADD reg
    Start and
    Stop bit detect
    SSPBUF reg
    Internal
    data bus
    Addr Match
    Set, Reset
    S, P bits
    (SSPSTAT reg)
    RC3/SCK/SCL
    RC4/
    shift
    clock
    MSb
    SDI/
    LSb
    SDA
    The SSPCON register allows control of the I2C opera-
    tion. Four mode selection bits (SSPCON<3:0>) allow
    one of the following I2C modes to be selected:
    I2C Slave mode (7-bit address)
    I2C Slave mode (10-bit address)
    I2C Slave mode (7-bit address), with start and
    stop bit interrupts enabled
    I2C Slave mode (10-bit address), with start and
    stop bit interrupts enabled
    I2C Firmware controlled Master Mode, slave is
    idle
    Selection of any I2C mode, with the SSPEN bit set,
    forces the SCL and SDA pins to be open drain, pro-
    vided these pins are programmed to inputs by setting
    the appropriate TRISC bits.
    The SSPSTAT register gives the status of the data
    transfer. This information includes detection of a
    START or STOP bit, species if the received byte was
    data or address if the next byte is the completion of
    10-bit address, and if this will be a read or write data
    transfer. The SSPSTAT register is read only.
    The SSPBUF is the register to which transfer data is
    written to or read from. The SSPSR register shifts the
    data in or out of the device. In receive operations, the
    SSPBUF and SSPSR create a doubled buffered
    receiver. This allows reception of the next byte to begin
    before reading the last byte of received data. When the
    complete byte is received, it is transferred to the
    SSPBUF register and ag bit SSPIF is set. If another
    complete byte is received before the SSPBUF register
    is read, a receiver overow has occurred and bit
    SSPOV (SSPCON<6>) is set and the byte in the
    SSPSR is lost.
    The SSPADD register holds the slave address. In 10-bit
    mode, the user first needs to write the high byte of the
    address (1111 0 A9 A8 0). Following the high byte
    address match, the low byte of the address needs to be
    loaded (A7:A0).
    Applicable Devices
    72 73 73A 74 74A 76 77
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