參數(shù)資料
型號: PIC16C662T-04E/TQ
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PQFP44
封裝: 10 X 10 MM, 1 MM HEIGHT, PLASTIC, TQFP-44
文件頁數(shù): 50/136頁
文件大?。?/td> 634K
代理商: PIC16C662T-04E/TQ
PIC16C64X & PIC16C66X
DS30559A-page 20
Preliminary
1996 Microchip Technology Inc.
TABLE 4-1:
SPECIAL FUNCTION REGISTERS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR,
PER
Value on
all other
resets(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
uuuu uuuu
02h
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
03h
STATUS
IRP(2)
RP1(2)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
04h
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
PORTA Data Latch when written: PORTA pins when read
--xx 0000
--xu 0000
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
06h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx
uuuu uuuu
06h
PORTD(3)
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx
uuuu uuuu
06h
PORTE(3)
RE2
RE1
RE0
---- -xxx
---- -uuu
0Ah
PCLATH
Write buffer for upper 5 bits of program counter
---0 0000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(4)
CMIF
00-- ----
0Dh-1Eh Unimplemented
1Fh
CMCON
C2OUT
C1OUT
CIS
CM2
CM1
CM0
00-- 0000
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h
STATUS
IRP(2)
RP1(2)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
PORTA Data Direction Register
--11 1111
86h
TRISB
PORTB Data Direction Register
1111 1111
86h
TRISC
PORTC Data Direction Register
1111 1111
86h
TRISD(3)
PORTD Data Direction Register
1111 1111
86h
TRISE(3)
IBF
OBF
IBOV
PSPMODE
TRISE2
TRISE1
TRISE0
0000 -111
8Ah
PCLATH
Write buffer for upper 5 bits of program counter
---0 0000
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
8Ch
PIE1
PSPIE(4)
CMIE
00-- ----
8Dh
Unimplemented
8Eh
PCON
MPEEN
PER
POR
BOR
u--- -qqq
u--- -uuu
8Fh-9Eh
Unimplemented
9Fh
VRCON
VREN
VROE
VRR
VR3
VR2
VR1
VR0
000- 0000
Legend: - = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note
1: Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: The IRP and RP1 bits are reserved, always maintain these bits clear.
3: The PORTD, PORTE, TRISD, and TRISE registers are not implemented on the PIC16C641/642.
4: Bits PSPIE and PSPIF are reserved on the PIC16C641/642, always maintain these bits clear.
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