
92
AT90S/LS4433
1042H–AVR–04/03
Reading the Signature Bytes
The algorithm for reading the signature bytes is as follows (refer to “Programming the
Flash” for details on command and address loading):
A: Load Command “0000 1000”.
B: Load Address Low Byte ($00 - $02).
1.
Set OE to “0”, and BS to “0”. The selected signature byte can now be read at
DATA.
2.
Set OE to “1”.
Parallel Programming
Characteristics
Figure 65. Parallel Programming Timing
Notes:
1. Use tWLWH_CE for Chip Erase and tWLWH_PFB for programming the Fuse bits.
2. If t
WLWH is held longer than tWLRH, no RDY/BSY pulse will be seen.
Table 33. Parallel Programming Characteristics T
A = 25°C ± 10%, VCC = 5V ± 10%
Symbol
Parameter
Min
Typ
Max
Units
V
PP
Programming Enable Voltage
11.5
12.5
V
IPP
Programming Enable Current
250.0
A
t
DVXH
Data and Control Setup before XTAL1 High
67.0
ns
t
XHXL
XTAL1 Pulse Width High
67.0
ns
tXLDX
Data and Control Hold after XTAL1 Low
67.0
ns
t
XLWL
XTAL1 Low to WR Low
67.0
ns
tBVWL
BS Valid to WR Low
67.0
ns
tRHBX
BS Hold after RDY/BSY High
67.0
ns
t
WLWH
67.0
ns
tWHRL
WR High to RDY/BSY Low
20.0
ns
tWLRH
WR Low to RDY/BSY High
0.5
0.7
0.9
ms
t
XLOL
XTAL1 Low to OE Low
67.0
ns
tOLDV
OE Low to DATA Valid
20.0
ns
tOHDZ
OE High to DATA Tri-stated
20.0
ns
t
WLWH_CE
WR Pulse Width Low for Chip Erase
5.0
10.0
15.0
ms
tWLWH_PFB
WR Pulse Width Low for Programming the Fuse
Bits
1.0
1.5
1.8
ms
Data & Contol
(DATA, XA0/1, BS)
DATA
W
rite
Read
XTAL1
t
XHXL
t
WLWH
t
DVXH
t
XLOL
t
OLDV
t
WHRL
t
WLRH
WR
RDY/BSY
OE
t
XLDX
t
XLWL
t
RHBX
t
OHDZ
t
BVWL