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    參數(shù)資料
    型號: PIC16C65AT-10I/PT
    廠商: Microchip Technology
    文件頁數(shù): 60/126頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 4KX14 PWM 44TQFP
    標準包裝: 1,200
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 10MHz
    連通性: I²C,SPI,UART/USART
    外圍設備: 欠壓檢測/復位,POR,PWM,WDT
    輸入/輸出數(shù): 33
    程序存儲器容量: 7KB(4K x 14)
    程序存儲器類型: OTP
    RAM 容量: 192 x 8
    電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
    振蕩器型: 外部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 44-TQFP
    包裝: 帶卷 (TR)
    1997 Microchip Technology Inc.
    DS30234D-page 39
    PIC16C6X
    FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch)
    FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch)
    R/W-0
    RCIE
    TXIE
    SSPIE
    CCP1IE
    TMR2IE
    TMR1IE
    R
    = Readable bit
    W = Writable bit
    U
    = Unimplemented bit,
    read as ‘0’
    - n = Value at POR reset
    bit7
    bit0
    bit 7-6:
    Reserved: Always maintain these bits clear.
    bit 5:
    RCIE: USART Receive Interrupt Enable bit
    1 = Enables the USART receive interrupt
    0 = Disables the USART receive interrupt
    bit 4:
    TXIE: USART Transmit Interrupt Enable bit
    1 = Enables the USART transmit interrupt
    0 = Disables the USART transmit interrupt
    bit 3:
    SSPIE: Synchronous Serial Port Interrupt Enable bit
    1 = Enables the SSP interrupt
    0 = Disables the SSP interrupt
    bit 2:
    CCP1IE: CCP1 Interrupt Enable bit
    1 = Enables the CCP1 interrupt
    0 = Disables the CCP1 interrupt
    bit 1:
    TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
    1 = Enables the TMR2 to PR2 match interrupt
    0 = Disables the TMR2 to PR2 match interrupt
    bit 0:
    TMR1IE: TMR1 Overow Interrupt Enable bit
    1 = Enables the TMR1 overow interrupt
    0 = Disables the TMR1 overow interrupt
    R/W-0
    U-0
    R/W-0
    PSPIE
    SSPIE
    CCP1IE
    TMR2IE
    TMR1IE
    R
    = Readable bit
    W = Writable bit
    U
    = Unimplemented bit,
    read as ‘0’
    - n = Value at POR reset
    bit7
    bit0
    bit 7:
    PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
    1 = Enables the PSP read/write interrupt
    0 = Disables the PSP read/write interrupt
    bit 6:
    Reserved: Always maintain this bit clear.
    bit 5-4:
    Unimplemented: Read as '0'
    bit 3:
    SSPIE: Synchronous Serial Port Interrupt Enable bit
    1 = Enables the SSP interrupt
    0 = Disables the SSP interrupt
    bit 2:
    CCP1IE: CCP1 Interrupt Enable bit
    1 = Enables the CCP1 interrupt
    0 = Disables the CCP1 interrupt
    bit 1:
    TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
    1 = Enables the TMR2 to PR2 match interrupt
    0 = Disables the TMR2 to PR2 match interrupt
    bit 0:
    TMR1IE: TMR1 Overow Interrupt Enable bit
    1 = Enables the TMR1 overow interrupt
    0 = Disables the TMR1 overow interrupt
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