- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10887 > PIC16C62BT-20E/SS (Microchip Technology)IC MCU OTP 2KX14 PWM 28SSOP PDF資料下載
參數(shù)資料
| 型號： | PIC16C62BT-20E/SS |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 61/120頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 2KX14 PWM 28SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，SPI |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 22 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁
PIC16C62B/72A
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 45
8.3.2
MASTER OPERATION
Master operation is supported in firmware using inter-
rupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared by a reset or when the SSP module is dis-
abled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I2C bus may be taken when the P bit is set, or the
bus is idle and both the S and P bits are clear.
In master operation, the SCL and SDA lines are manip-
ulated in software by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So when
transmitting data, a ’1’ data bit must have the
TRISC<4> bit set (input) and a ’0’ data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
START condition
STOP condition
Byte transfer completed
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see
AN554
- Software Implementation of I2C Bus Master.
8.3.3
MULTI-MASTER OPERATION
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
Address Transfer
Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
For more information on master operation, see
AN578
- Use of the SSP Module in the of I2C Multi-Master
Environment.
TABLE 8-3
REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
resets
0Bh, 8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
SSPIF
CCP1IF TMR2IF TMR1IF
-0-- 0000
8Ch
PIE1
—
ADIE
—
SSPIE CCP1IE TMR2IE TMR1IE
-0-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
14h
SSPCON
WCOL
SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0
0000 0000
94h
SSPSTAT
SMP(1)
CKE(1)
D/A
PS
R/W
UA
BF
0000 0000
87h
TRISC
PORTC Data Direction register
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1:
Maintain these bits clear in I2C mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC16C62BT-20E/SO | IC MCU OTP 2KX14 PWM 28SOIC |
| PIC16C62BT-04/SS | IC MCU OTP 2KX14 PWM 28SSOP |
| PIC16C62BT-04/SO | IC MCU OTP 2KX14 PWM 28SOIC |
| PIC16C62BT-04I/SO | IC MCU OTP 2KX14 PWM 28SOIC |
| PIC16C62BT-04E/SS | IC MCU OTP 2KX14 PWM 28SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16C62BT-20I/ML | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C62BT-20I/SO | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C62BT-20I/SS | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C63/JW | 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| PIC16C63-04/SO | 功能描述:8位微控制器 -MCU 7KB 192 RAM 22 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。