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| 鍨嬭櫉锛� | PIC16C62B-04/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/120闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 2KX14 PWM 28SSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 47 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣嶏紝POR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 22 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 3.5KB锛�2K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 28-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 636 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164307-ND - MODULE SKT FOR PM3 28SSOP 309-1025-ND - ADAPTER 28-SSOP TO 28-DIP |
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PIC16C62B/72A
DS35008B-page 100
Preliminary
1998 Microchip Technology Inc.
FIGURE 13-16: I2C BUS DATA TIMING
TABLE 13-12: I2C BUS DATA REQUIREMENTS
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
100*
THIGH
Clock high time
100 kHz mode
4.0
鈥�
s
Device must operate at a min-
imum of 1.5 MHz
400 kHz mode
0.6
鈥�
s
Device must operate at a min-
imum of 10 MHz
SSP Module
1.5TCY
鈥�
101*
TLOW
Clock low time
100 kHz mode
4.7
鈥�
s
Device must operate at a min-
imum of 1.5 MHz
400 kHz mode
1.3
鈥�
s
Device must operate at a min-
imum of 10 MHz
SSP Module
1.5TCY
鈥�
102*
TR
SDA and SCL rise
time
100 kHz mode
鈥�
1000
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specified to be from
10-400 pF
103*
TF
SDA and SCL fall
time
100 kHz mode
鈥�
300
ns
400 kHz mode
20 + 0.1Cb
300
ns
Cb is specified to be from
10-400 pF
90*
TSU:STA
START condition
setup time
100 kHz mode
4.7
鈥�
s
Only relevant for repeated
START condition
400 kHz mode
0.6
鈥�
s
91*
THD:STA
START condition hold
time
100 kHz mode
4.0
鈥�
s
After this period the first clock
pulse is generated
400 kHz mode
0.6
鈥�
s
106*
THD:DAT
Data input hold time
100 kHz mode
0
鈥�
ns
400 kHz mode
0
0.9
s
107*
TSU:DAT
Data input setup time
100 kHz mode
250
鈥�
ns
Note 2
400 kHz mode
100
鈥�
ns
92*
TSU:STO
STOP condition setup
time
100 kHz mode
4.7
鈥�
s
400 kHz mode
0.6
鈥�
s
109*
TAA
Output valid from
clock
100 kHz mode
鈥�
3500
ns
Note 1
400 kHz mode
鈥�
ns
110*
TBUF
Bus free time
100 kHz mode
4.7
鈥�
s
Time the bus must be free
before a new transmission
can start
400 kHz mode
1.3
鈥�
s
Cb
Bus capacitive loading
鈥�
400
pF
*
These parameters are characterized but not tested.
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the fall-
ing edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT
鈮�
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released.
Note:
Refer to Figure 13-4 for load conditions.
90
91
92
100
101
103
106
107
109
110
102
SCL
SDA
In
SDA
Out
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