鈫� 1
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC16C621A-04/P
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 61/89闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU OTP 1KX14 COMP 18DIP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 25
绯诲垪锛� PIC® 16C
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 4MHz
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孭OR锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 13
绋嬪簭瀛樺劜鍣ㄥ閲忥細 1.75KB锛�1K x 14锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 OTP
RAM 瀹归噺锛� 96 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.5 V ~ 5.5 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 18-DIP锛�0.300"锛�7.62mm锛�
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 636 (CN2011-ZH PDF)
閰嶇敤锛� ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
AC164010-ND - MODULE SKT PROMATEII DIP/SOIC
64
AT90S1200
0838H鈥揂VR鈥�03/02
BIT AND BIT-TEST INSTRUCTIONS
SBI
P, b
Set Bit in I/O Register
I/O(P,b)
鈫� 1
None
2
CBI
P, b
Clear Bit in I/O Register
I/O(P,b)
鈫� 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1)
鈫� Rd(n), Rd(0) 鈫� 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n)
鈫� Rd(n+1), Rd(7) 鈫� 0
Z,C,N,V
1
ROL
Rd
Rotate Left through Carry
Rd(0)
鈫� C,Rd(n+1) 鈫� Rd(n),C 鈫� Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right through Carry
Rd(7)
鈫� C,Rd(n) 鈫� Rd(n+1),C 鈫� Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
鈫� Rd(n+1), n = 0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
鈫� Rd(7..4),Rd(7..4) 鈫� Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s)
鈫� 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
鈫� 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T
鈫� Rr(b)
T
1
BLD
Rd, b
Bit Load from T to Register
Rd(b)
鈫� T
None
1
SEC
Set Carry
C
鈫� 1C
1
CLC
Clear Carry
C
鈫� 0C
1
SEN
Set Negative Flag
N
鈫� 1N
1
CLN
Clear Negative Flag
N
鈫� 0N
1
SEZ
Set Zero Flag
Z
鈫� 1Z
1
CLZ
Clear Zero Flag
Z
鈫� 0Z
1
SEI
Global Interrupt Enable
I
鈫� 1I
1
CLI
Global Interrupt Disable
I
鈫� 0I
1
SES
Set Signed Test Flag
S
鈫� 1S
1
CLS
Clear Signed Test Flag
S
鈫� 0S
1
SEV
Set Two鈥檚 Complement Overflow
V
鈫� 1V
1
CLV
Clear Two鈥檚 Complement Overflow
V
鈫� 0V
1
SET
Set T in SREG
T
鈫� 1T
1
CLT
Clear T in SREG
T
鈫� 0T
1
SEH
Set Half-carry Flag in SREG
H
鈫� 1H
1
CLH
Clear Half-carry Flag in SREG
H
鈫� 0H
1
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
Watchdog Reset
(see specific descr. for WDR/timer)
None
1
Instruction Set Summary (Continued)
Mnemonic
Operands
Description
Operation
Flags
# Clocks
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
PIC16C54C-20/SO IC MCU OTP 512X12 18SOIC
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
PIC16C621A-20/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.75KB 96 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC16C621A-20/P 鍒堕€犲晢:Microchip Technology Inc 鍔熻兘鎻忚堪:IC 8BIT CMOS MCU 16C621 DIP18
PIC16C621A-20/SO 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.75KB 96 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC16C621A-20/SS 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.75KB 96 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
PIC16C621A-20E/P 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 1.75KB 96 RAM 13 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT