
PIC18F2450/4450
2006 Microchip Technology Inc.
Advance Information
DS39760A-page 161
FIGURE 15-1:
AUTOMATIC BAUD RATE CALCULATION
FIGURE 15-2:
BRG OVERFLOW SEQUENCE
BRG Value
RX pin
ABDEN bit
RCIF bit
bit 0
bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Auto-Cleared
Set by User
XXXXh
0000h
Edge #1
bit 2
bit 3
Edge #2
bit 4
bit 5
Edge #3
bit 6
bit 7
Edge #4
Edge #5
001Ch
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
SPBRG
XXXXh
1Ch
SPBRGH
XXXXh
00h
Stop bit
Start
bit 0
XXXXh
0000h
FFFFh
BRG Clock
ABDEN bit
RX pin
ABDOVF bit
BRG Value