• 參數(shù)資料
    型號: PIC16C54C-04/P
    廠商: Microchip Technology
    文件頁數(shù): 181/194頁
    文件大?。?/td> 0K
    描述: IC MCU OTP 512X12 18DIP
    產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
    8-bit PIC® Microcontroller Portfolio
    標(biāo)準(zhǔn)包裝: 25
    系列: PIC® 16C
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 4MHz
    外圍設(shè)備: POR,WDT
    輸入/輸出數(shù): 12
    程序存儲器容量: 768B(512 x 12)
    程序存儲器類型: OTP
    RAM 容量: 25 x 8
    電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
    振蕩器型: 外部
    工作溫度: 0°C ~ 70°C
    封裝/外殼: 18-DIP(0.300",7.62mm)
    包裝: 管件
    配用: 309-1059-ND - ADAPTER 18 ZIF BD W/18SO PLUGS
    DVA16XP180-ND - ADAPTER DEVICE FOR MPLAB-ICE
    AC164001-ND - MODULE SKT PROMATEII 18/28DIP
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    PIC18F2450/4450
    2006 Microchip Technology Inc.
    Advance Information
    DS39760A-page 85
    8.0
    INTERRUPTS
    The PIC18F2450/4450 devices have multiple interrupt
    sources and an interrupt priority feature that allows
    each interrupt source to be assigned a high priority
    level or a low priority level. The high priority interrupt
    vector is at 000008h and the low priority interrupt vector
    is at 000018h. High priority interrupt events will
    interrupt any low priority interrupts that may be in
    progress.
    There are ten registers which are used to control
    interrupt operation. These registers are:
    RCON
    INTCON
    INTCON2
    INTCON3
    PIR1, PIR2
    PIE1, PIE2
    IPR1, IPR2
    It is recommended that the Microchip header files
    supplied with MPLAB IDE be used for the symbolic bit
    names in these registers. This allows the assembler/
    compiler to automatically take care of the placement of
    these bits within the specified register.
    Each interrupt source has three bits to control its
    operation. The functions of these bits are:
    Flag bit to indicate that an interrupt event
    occurred
    Enable bit that allows program execution to
    branch to the interrupt vector address when the
    flag bit is set
    Priority bit to select high priority or low priority
    The interrupt priority feature is enabled by setting the
    IPEN bit (RCON<7>). When interrupt priority is
    enabled, there are two bits which enable interrupts
    globally. Setting the GIEH bit (INTCON<7>) enables all
    interrupts that have the priority bit set (high priority).
    Setting the GIEL bit (INTCON<6>) enables all
    interrupts that have the priority bit cleared (low priority).
    When the interrupt flag, enable bit and appropriate
    global interrupt enable bit are set, the interrupt will
    vector immediately to address 000008h or 000018h,
    depending on the priority bit setting. Individual inter-
    rupts can be disabled through their corresponding
    enable bits.
    When the IPEN bit is cleared (default state), the
    interrupt priority feature is disabled and interrupts are
    compatible with PICmicro mid-range devices. In
    Compatibility mode, the interrupt priority bits for each
    source have no effect. INTCON<6> is the PEIE bit
    which enables/disables all peripheral interrupt sources.
    INTCON<7> is the GIE bit which enables/disables all
    interrupt sources. All interrupts branch to address
    000008h in Compatibility mode.
    When an interrupt is responded to, the global interrupt
    enable bit is cleared to disable further interrupts. If the
    IPEN bit is cleared, this is the GIE bit. If interrupt priority
    levels are used, this will be either the GIEH or GIEL bit.
    High priority interrupt sources can interrupt a low
    priority interrupt. Low priority interrupts are not
    processed while high priority interrupts are in progress.
    The return address is pushed onto the stack and the PC
    is loaded with the interrupt vector address (000008h or
    000018h). Once in the Interrupt Service Routine, the
    source(s) of the interrupt can be determined by polling
    the interrupt flag bits. The interrupt flag bits must be
    cleared in software before re-enabling interrupts to avoid
    recursive interrupts.
    The “return from interrupt” instruction, RETFIE, exits
    the interrupt routine and sets the GIE bit (GIEH or GIEL
    if priority levels are used) which re-enables interrupts.
    For external interrupt events, such as the INT pins or
    the PORTB input change interrupt, the interrupt latency
    will be three to four instruction cycles. The exact
    latency is the same for one or two-cycle instructions.
    Individual interrupt flag bits are set regardless of the
    status of their corresponding enable bit or the GIE bit.
    8.1
    USB Interrupts
    Unlike other peripherals, the USB module is capable of
    generating a wide range of interrupts for many types of
    events. These include several types of normal commu-
    nication and status events and several module level
    error events.
    To handle these events, the USB module is equipped
    with its own interrupt logic. The logic functions in a
    manner similar to the microcontroller level interrupt
    funnel, with each interrupt source having separate flag
    and enable bits. All events are funneled to a single
    device level interrupt, USBIF (PIR2<5>). Unlike the
    device level interrupt logic, the individual USB interrupt
    events cannot be individually assigned their own prior-
    ity. This is determined at the device level interrupt
    funnel for all USB events by the USBIP bit.
    For additional details on USB interrupt logic, refer to
    Note:
    Do not use the MOVFF instruction to modify
    any of the interrupt control registers while
    any interrupt is enabled. Doing so may
    cause erratic microcontroller behavior.
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