參數(shù)資料
型號: PIC16C505-04/P
廠商: Microchip Technology
文件頁數(shù): 11/90頁
文件大小: 0K
描述: IC MCU OTP 1KX12 14DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 30
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 11
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: OTP
RAM 容量: 72 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: 0°C ~ 70°C
封裝/外殼: 14-DIP(0.300",7.62mm)
包裝: 管件
配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1086-ND - ADAPTER 14-ZIF BD W/14-SO PLUGS
309-1085-ND - ADAPTER 14-DIP BD W/2 14-SO PLUG
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
1999-2012 Microchip Technology Inc.
DS40192D-page 19
PIC16C505
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF PORTB,W) always read
the I/O pins independent of the pin’s input/output
modes. On RESET, all I/O ports are defined as input
(inputs are at hi-impedance) since the I/O control
registers are all set.
5.1
PORTB
PORTB is an 8-bit I/O register. Only the low order 6
bits
are
used
(RB<5:0>).
Bits
7
and
6
are
unimplemented and read as '0's. Please note that RB3
is an input only pin. The configuration word can set
several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during port
read. Pins RB0, RB1, RB3 and RB4 can be configured
with weak pull-ups and also with wake-up on change.
The wake-up on change and weak pull-up functions
are not pin selectable. If pin 4 is configured as MCLR,
weak pull-up is always off and wake-up on change for
this pin is not enabled.
5.2
PORTC
PORTC is an 8-bit I/O register. Only the low order 6 bits
are used (RC<5:0>). Bits 7 and 6 are unimplemented
and read as ‘0’s.
5.3
TRIS Registers
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected
pins,
enabling
the
output
buffer.
The
exceptions are RB3, which is input only, and RC5,
which may be controlled by the option register. See
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
5.4
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins except RB3, which is input
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF PORTB,W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except RB3) can be programmed individually as
input or output.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
P
N
WR
Port
TRIS ‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin(1)
W
Reg
Latch
Reset
Note 1:
I/O pins have protection diodes to VDD and VSS.
Note 2:
See Table 3-1 for buffer type.
(2)
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