參數(shù)資料
型號(hào)： PIC14000-04/SP
廠商： Microchip Technology
文件頁數(shù)： 102/153頁
文件大?。?/td> 0K
描述： IC MCU OTP 4KX14 A/D 28DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 15
系列： PIC® 14
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
連通性： I²C
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 20
程序存儲(chǔ)器容量： 7KB（4K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器： 斜率 A/D
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 28-DIP（0.300"，7.62mm）
包裝： 管件
配用： ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
PIC14000
DS40122B-page 52
Preliminary
1996 Microchip Technology Inc.
7.5.2
MASTER MODE
Master mode operation is supported by interrupt
generation on the detection of the START and STOP.
The STOP(P) and START(S) bits are cleared from a
reset or when the I2C module is disabled. Control of the
I2C bus may be taken when the P bit is set, or the bus
is idle and both the S and P bits are cleared.
In master mode, the SCL and SDA lines are
manipulated
by
changing
the
corresponding
TRISC<7:6> or TRISD<1:0> bits to an output (cleared).
The output level is always low, regardless of the
value(s) in PORTC<7:6> or PORTD<1:0>. So when
transmitting data, a “1” data bit must have the
TRISC<7> or TRISD<1> bit set (input) and a “0” data
bit must have the TRISC<7> or TRISD<1> bit cleared
(output). The same scenario is true for the SCL line
with the TRISC<6> or TRISD<0> bit.
The following events will cause the I2C interrupt Flag
(I2CIF) to be set (I2C interrupt if enabled):
START
STOP
Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (I2CM3...I2CM0 = 1011b) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
7.5.3
MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP allows the
determination of when the bus is free. The STOP (P)
and START (S) bits are cleared from a reset or when
the I2C module is disabled. Control of the I2C bus may
be taken when the P bit is set, or the bus is idle and
both the S and P bits are cleared. When the bus is
busy, enabling the I2C interrupt will generate the
interrupt when the STOP occurs.
In multi-master operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and low
level is present, the device needs to release the SDA
and SCL lines (set TRISC<7:6>). There are two stages
where this arbitration can be lost, these are:
Address Transfer
Data Transfer
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address
transfer stage, the device may being addressed. If
addressed an ACK pulse will be generated. If
arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
TABLE 7-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0B/8Bh
INTCON
GIE
PEIE
T0IE
r
T0IF
r
0Ch
PIR1
CMIF
—
PBIF
I2CIF
RCIF
ADCIF
OVFIF
8Ch
PIE1
CMIE
—
PBIE
I2CIE
RCIE
ADCIE
OVFIE
13h
I2CBUF
I2C Serial Port Receive Buffer/Transmit Register
93h
I2CADD
I2C mode Synchronous Serial Port (I2C mode) Address Register
14h
I2CCON
WCOL
I2CON
I2CEN
CKP
I2CM3
I2CM2
I2CM1
I2CM0
94h
I2CSTAT
—
D/A
P
S
R/W
UA
BF
9Eh
MISC
SMHOG
SPGNDB
SPGNDA
I2CSEL
SMBUS
INCLKEN
OSC2
OSC1
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
88h
TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
Legend:
— = Unimplemented location, read as ‘0’
r = reserved locations, default is POR value and should not be overwritten with any value
Note: Shaded boxes are not used by the I2C module.
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