參數(shù)資料
型號(hào): PIC12LF1822-I/MF
廠商: Microchip Technology
文件頁(yè)數(shù): 56/109頁(yè)
文件大小: 0K
描述: IC MCU 8BIT FLASH 8DFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 120
系列: PIC® XLP™ 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 6
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-VDFN 裸露焊盤
包裝: 管件
241
7674F–AVR–09/09
ATmega164P/324P/644P
20.3
Register Description
20.3.1
ADCSRB – ADC Control and Status Register B
Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
20.3.2
ACSR – Analog Comparator Control and Status Register
Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog
Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-
ator. When bandgap reference is used as input to the Analog Comparator, it will take a certain
time for the voltage to stabilize. If not stabilized, the first conversion may give wrong value. See
Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 - 2 clock cycles.
10
001
ADC1
10
010
ADC2
10
011
ADC3
10
100
ADC4
10
101
ADC5
10
110
ADC6
10
111
ADC7
Table 20-1.
Analog Comparator Mulitiplexed Input
ACME
ADEN
MUX2..0
Analog Comparator Negative Input
Bit
7
65
432
10
ACME
MUX5
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R
R/W
R
R/W
Initial Value
0
Bit
76543210
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
Initial Value
0
N/A
00000
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