參數(shù)資料
型號(hào)： PIC12F635-I/P
廠商： Microchip Technology
文件頁數(shù)： 39/74頁
文件大?。?/td> 0K
描述： IC MCU FLASH 1KX14 8DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 60
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 128 x 8
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-DIP（0.300"，7.62mm）
包裝： 管件
產(chǎn)品目錄頁面： 637 (CN2011-ZH PDF)
配用： DM163029-ND - BOARD PICDEM FOR MECHATRONICS
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
ACICE0201-ND - MPLABICE 8P 300 MIL ADAPTER
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
Micrel, Inc.
KSZ8841-PMQL
October 2007
44
M9999-100407-1.5
These three registers value for MAC address 01:23:45:67:89:AB will be held as below:
MARL[15:0] = 0x89AB
MARM[15:0] = 0x4567
MARH[15:0] = 0x0123
The following table shows the register bit fields for low word of MAC address.
Bit
Default
R/W
Description
15-0
-
RW
MARL MAC Address Low
The least significant word of the MAC address
MAC Address Register Middle (0x0202): MARM
The following table shows the register bit fields for middle word of MAC address.
Bit
Default
R/W
Description
15-0
-
RW
MARM MAC Address Middle
The middle word of the MAC address
MAC Address Register High (0x0204): MARH
The following table shows the register bit fields for high word of MAC address.
Bit
Default
R/W
Description
15-0
-
RW
MARH MAC Address High
The Most significant word of the MAC address
On-Chip Bus Control Register (Offset 0x0210): OBCR
This register controls the on-chip bus speed for the KSZ8841-PMQL operations. It’s used for power management when
the external host CPU is running a slow frequency. The default of the on-chip bus speed is 25MHz. When the external
host CPU is running at a higher clock rate, it’s recommended the on-chip bus is adjusted accordingly for the best
performance.
Bit
Default
R/W
Description
15-2
-
RO
Reserved
1-0
0x3
RW
OBSC On-Chip Bus Speed Control
00: 125 MHz
01: 62.5 MHz
10: 41.66 MHz
11: 25 MHz
EEPROM Control Register (Offset 0x0212): EEPCR
KSZ8841-PMQL supports both with and without EEPROM system design. To support external EEPROM, tie the
EEPROM Enable (EEEN) pin to high; otherwise, tie it to Low (or no connect). Also, KSZ8841-PMQL allows software to
access (read and write) EEPROM directly. That is, the EEPROM access timing can be fully controlled by software if
EEPROM Software Access bit is set.
Bit
Default
R/W
Description
15-5
0
RO
Reserved
4
0
RW
EESA EEPROM Software Access
1 = Enable software to access EEPROM through bit 14 to bit 11.
0 = Disable software to access EEPROM.
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