參數(shù)資料
型號: PIC12F519-I/MS
廠商: Microchip Technology
文件頁數(shù): 10/96頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 1KX12 8MSOP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 100
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
外圍設備: POR,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 1.5KB(1K x 12)
程序存儲器類型: 閃存
RAM 容量: 41 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 637 (CN2011-ZH PDF)
配用: AC162096-ND - HEADER MPLAB ICD2 PIC16F526 8/14
AC164325-ND - MODULE SKT FOR 8MSOP
PIC12F519
DS41319B-page 16
2008 Microchip Technology Inc.
4.3
STATUS register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS, will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWF
instructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions which
do affect Status bits, see Section 9.0 “Instruction Set
REGISTER 4-1:
STATUS: STATUS REGISTER
R/W-0
U-0
R/W-0
R-1
R/W-x
GPWUF
—PA0
TO
PD
ZDC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GPWUF
: Wake-up From Sleep on Pin Change bit
1
= Reset due to wake-up from Sleep on pin change
0
= After power-up or other Reset
bit 6
Unimplemented:
Read as ‘0
bit 5
PA0
: Program Page Preselect bit
1
= Page 1 (000h-1FFh)
0
= Page 0 (200h-3FFh)
bit 4
TO
: Time-out bit
1
= After power-up, CLRWDT instruction, or SLEEP instruction
0
= A WDT time-out occurred
bit 3
PD
: Power-down bit
1
= After power-up or by the CLRWDT instruction
0
= By execution of the SLEEP instruction
bit 2
Z
: Zero bit
1
= The result of an arithmetic or logic operation is zero
0
= The result of an arithmetic or logic operation is not zero
bit 1
DC
: Digit carry/borrow bit (for ADDWF and SUBWF instructions)
ADDWF:
1
= A carry from the 4th low-order bit of the result occurred
0
= A carry from the 4th low-order bit of the result did not occur
SUBWF:
1
= A borrow from the 4th low-order bit of the result did not occur
0
= A borrow from the 4th low-order bit of the result occurred
bit 0
C
: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)
ADDWF:
SUBWF:
RRF
or RLF:
1
= A carry occurred
1
= A borrow did not occur
Load bit with LSb or MSb, respectively
0
= A carry did not occur
0
= A borrow occurred
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