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參數(shù)資料
| 型號(hào)： | PIC12F1840T-I/MF |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 114/122頁(yè) |
| 文件大小： | 0K |
| 描述： | MCU 7KB FLASH 256B RAM XLP 8DFN |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® XLP™ 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 32MHz |
| 連通性： | I²C，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 7KB（4K x 14） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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2011 Microchip Technology Inc.
Preliminary
DS41441B-page 91
PIC12(L)F1840
9.2
Low Power Sleep Mode
The PIC12F1840 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC12F1840 allows the user to optimize the operating
current in Sleep, depending on the application require-
ments.
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
9.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal con-
figuration and stabilize.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
9.2.2
PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the normal power
mode when those peripherals are enabled. The Low-
Power Sleep mode is intended for use with these
peripherals:
Brown-Out Reset (BOR)
Watchdog Timer (WDT)
External interrupt pin/Interrupt-on-change pins
Timer1 (with external clock source)
Comparator
ECCP (Capture mode)
Note:
The PIC12LF1840 does not have a con-
figurable
Low-Power
Sleep
mode.
PIC12LF1840 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time pen-
alty. This device has a lower maximum
VDD
and
I/O
voltage
than
the
PIC12F1840. See Section 30.0 “Electri-
for more information.
REGISTER 9-1:
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
R/W-0/0
R/W-1/1
—
—VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-2
Unimplemented:
Read as ‘0’
bit 1
VREGPM:
Voltage Regulator Power Mode Selection bit
1
= Low Power Sleep mode enabled in Sleep
Draws lowest current in Sleep, slower wake-up
0
= Normal Power mode enabled in Sleep
Draws higher current in Sleep, faster wake-up
bit 0
Reserved:
Read as ‘1’. Maintain this bit set.
Note 1:
PIC12F1840 only.
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