參數(shù)資料
型號: PIC12F1840-I/SN
廠商: Microchip Technology
文件頁數(shù): 109/122頁
文件大?。?/td> 0K
描述: MCU 7KB FLASH 256B RAM 8-SOIC
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 100
系列: PIC® XLP™ 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 32MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 5
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 管件
2011 Microchip Technology Inc.
Preliminary
DS41441B-page 87
PIC12(L)F1840
8.5.5
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 8-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
software
should
ensure
the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 8-5:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
U-0
R/W-0/0
U-0
OSFIF
C1IF
EEIF
BCL1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
OSFIF:
Oscillator Fail Interrupt Flag bit
1
= Interrupt is pending
0
= Interrupt is not pending
bit 6
Unimplemented:
Read as ‘0’
bit 5
C1IF:
Comparator C1 Interrupt Flag bit
1
= Interrupt is pending
0
= Interrupt is not pending
bit 4
EEIF:
EEPROM Write Completion Interrupt Flag bit
1
= Interrupt is pending
0
= Interrupt is not pending
bit 3
BCL1IF:
MSSP Bus Collision Interrupt Flag bit
1
= Interrupt is pending
0
= Interrupt is not pending
bit 2-0
Unimplemented:
Read as ‘0’
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