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參數(shù)資料
| 型號(hào)： | PIC12CE674/JW |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 89/129頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU EPROM 2KX14 A/D&EE 8CDIP |
| 標(biāo)準(zhǔn)包裝： | 56 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 10MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 3.5KB（2K x 14） |
| 程序存儲(chǔ)器類(lèi)型： | EPROM，UV |
| EEPROM 大?。?/td> | 16 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-CDIP（0.300"，7.62mm）窗口 |
| 包裝： | 管件 |
| 配用： | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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PIC12C67X
DS30561B-page 62
1999 Microchip Technology Inc.
9.5
Interrupts
There are four sources of interrupt:
The Interrupt Control Register (INTCON) records indi-
vidual interrupt requests in flag bits. It also has individ-
ual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt flag bits are set,
regardless of the status of their corresponding mask bit
or the GIE bit. The GIE bit is cleared on reset.
Interrupt Sources
TMR0 Overflow Interrupt
External Interrupt GP2/INT pin
GPIO Port Change Interrupts (pins GP0, GP1, GP3)
A/D Interrupt
Note:
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
The “return-from-interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag ADIF, is contained in the
Special Function Register PIR1. The corresponding
interrupt enable bit is contained in Special Function
Register PIE1, and the peripheral interrupt enable bit is
contained in Special Function Register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid repeated interrupts.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends on when
the interrupt event occurs (Figure 9-14). The latency is
the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 9-13: INTERRUPT LOGIC
GPIF
GPIE
T0IF
T0IE
GIE
Wake-up
(If in SLEEP mode)
Interrupt to CPU
PEIE
ADIF
ADIE
INTF
INTE
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