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| 型號(hào)： | PIC12C672-04I/SM |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 48/129頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 2KX14 A/D 8-SOIJ |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲(chǔ)器容量： | 3.5KB（2K x 14） |
| 程序存儲(chǔ)器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 配用： | XLT08SO-1-ND - SOCKET TRANSITION 8SOIC 150/208 AC164312-ND - MODULE SKT FOR PM3 16SOIC ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1048-ND - ADAPTER 8-SOIC TO 8-DIP 309-1047-ND - ADAPTER 8-SOIC TO 8-DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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1999 Microchip Technology Inc.
DS30561B-page 25
PIC12C67X
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However, read
instructions (i.e., MOVF GPIO,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance), since the I/O control registers are all
set.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP<5:0>). Bits 6 and 7 (SDA and SCL,
respectively) are used by the EEPROM peripheral on
the PIC12CE673/674.
Refer to Section 6.0 and
Appendix B for use of SDA and SCL. Please note that
GP3 is an input only pin. The configuration word can
set several I/O’s to alternate functions. When acting as
alternate functions, the pins will read as ‘0’ during port
read. Pins GP0, GP1 and GP3 can be configured with
weak pull-ups and also with interrupt-on-change. The
interrupt on change and weak pull-up functions are not
pin selectable. If pin 4, (GP3), is configured as MCLR,
a weak pull-up is always on. Interrupt-on-change for
this pin is not set and GP3 will read as '0'. Interrupt-on-
change is enabled by setting bit GPIE, INTCON<3>.
Note that external oscillator use overrides the GPIO
functions on GP4 and GP5.
5.2
TRIS Register
This register controls the data direction for GPIO. A '1'
from a TRIS Register bit puts the corresponding output
driver in a hi-impedance mode. A '0' puts the contents
of the output data latch on the selected pins, enabling
the output buffer. The exceptions are GP3, which is
input only and its TRIS bit will always read as '1', while
GP6 and GP7 TRIS bits will read as ’0’.
Upon reset, the TRIS Register is all '1's, making all
pins inputs.
TRIS for pins GP4 and GP5 is forced to a ’1’ where
appropriate. Writes to TRIS <5:4> will have an effect
in EXTRC and INTRC oscillator modes only. When
GP4 is configured as CLKOUT, changes to TRIS<4>
will have no effect.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1 through Figure 5-5. All port pins, except
GP3, which is input only, may be used for both input
and output operations. For input operations, these
ports are non-latching. Any input must be present until
read by an input instruction (i.e., MOVF GPIO,W). The
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
Port pins GP6 (SDA) and GP7 (SCL) are used for the
serial EEPROM interface on the PIC12CE673/674.
These port pins are not available externally on the
package.
Users should avoid writing to pins GP6
(SDA) and GP7 (SCL) when not communicating with
the serial EEPROM memory. Please see Section 6.0,
EEPROM Peripheral Operation, for information on
serial EEPROM communication.
Note:
On a Power-on Reset, GP0, GP1, GP2
and GP4 are configured as analog inputs
and read as '0'.
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