參數(shù)資料
型號(hào)： PIC12C672-04/SM
廠(chǎng)商： Microchip Technology
文件頁(yè)數(shù)： 91/129頁(yè)
文件大?。?/td> 0K
描述： IC MCU OTP 2KX14 A/D 8-SOIJ
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 90
系列： PIC® 12C
核心處理器： PIC
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 3.5KB（2K x 14）
程序存儲(chǔ)器類(lèi)型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 8-SOIC（0.209"，5.30mm 寬）
包裝： 管件
配用： XLT08SO-1-ND - SOCKET TRANSITION 8SOIC 150/208
AC164312-ND - MODULE SKT FOR PM3 16SOIC
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
309-1048-ND - ADAPTER 8-SOIC TO 8-DIP
309-1047-ND - ADAPTER 8-SOIC TO 8-DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
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PIC12C67X
DS30561B-page 64
1999 Microchip Technology Inc.
9.5.1
TMR0 INTERRUPT
An overflow (FFh
→ 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>)
The
flag
bit
T0IF
(INTCON<2>) will be set, regardless of the state of the
enable bits. If used, this flag must be cleared in software.
9.5.2
INT INTERRUPT
External interrupt on GP2/INT pin is edge triggered;
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
on
the
GP2/INT
pin,
flag
bit
INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
9.5.3
GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit GPIF
(INTCON<0>). The interrupt can be enabled/disabled by
setting/clearing
enable
bit
GPIE
(INTCON<3>)
(Section 5.1) . This flag bit GPIF (INTCON<0>) will be
set, regardless of the state of the enable bits. If used, this
flag must be cleared in software.
9.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-1 shows the storing and restoring of the
STATUS and W registers. The register, W_TEMP, must
be defined in both banks and must be defined at the
same offset from the bank base address (i.e., if
W_TEMP is defined at 0x20 in bank 0, it must also be
defined at 0xA0 in bank 1).
Example 9-2 shows the saving and restoring of STA-
TUS and W using RAM locations 0x70 - 0x7F.
W_TEMP is defined at 0x70 and STATUS_TEMP is
defined at 0x71.
The example:
a)
Stores the W register.
b)
Stores the STATUS register in bank 0.
c)
Executes the ISR code.
d)
Restores the STATUS register (and bank select
bit).
e)
Restores the W register.
f)
Returns from interrupt.
EXAMPLE 9-1:
SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM
(0x20 - 0x6F)
MOVWF
W_TEMP
;Copy W to TEMP register, could be bank one or zero
SWAPF
STATUS,W
;Swap status to be saved into W
BCF
STATUS,RP0
;Change to bank zero, regardless of current bank
MOVWF
STATUS_TEMP
;Save status to bank zero STATUS_TEMP register
:
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
MOVWF
STATUS
;Move W into STATUS register
SWAPF
W_TEMP,F
;Swap W_TEMP
SWAPF
W_TEMP,W
;Swap W_TEMP into W
RETFIE
;Return from interrupt
EXAMPLE 9-2:
SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)
MOVWF
W_TEMP
;Copy W to TEMP register (bank independent)
MOVF
STATUS,W
;Move STATUS register into W
MOVWF
STATUS_TEMP
;Save contents of STATUS register
:
:(ISR)
:
MOVF
STATUS_TEMP,W
;Retrieve copy of STATUS register
MOVWF
STATUS
;Restore pre-isr STATUS register contents
SWAPF
W_TEMP,F
;
SWAPF
W_TEMP,W
;Restore pre-isr W register contents
RETFIE
;Return from interrupt
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