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| 鍨嬭櫉(h脿o)锛� | PIC12C671-10I/P |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 10/129闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC MCU OTP 1KX14 A/D 8DIP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 绯诲垪锛� | PIC® 12C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 10MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 5 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 1.75KB锛�1K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 3 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 4x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 8-DIP锛�0.300"锛�7.62mm锛� |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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1999 Microchip Technology Inc.
DS30561B-page 107
PIC12C67X
TABLE 12-9:
EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE673/674
ONLY.
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0
掳C 鈮� TA 鈮� +70掳C, Vcc = 3.0V to 5.5V (commercial)
鈥�40
掳C 鈮� TA 鈮� +85掳C, Vcc = 3.0V to 5.5V (industrial)
鈥�40
掳C 鈮� TA 鈮� +125掳C, Vcc = 4.5V to 5.5V (extended)
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
FCLK
鈥�
100
400
kHz
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
Clock high time
THIGH
4000
600
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
Clock low time
TLOW
4700
1300
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
SDA and SCL rise time
TR
鈥�
1000
300
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
SDA and SCL fall time
TF
鈥�
300
ns
START condition hold time
THD:STA
4000
600
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
START condition setup time
TSU:STA
4700
600
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
Data input hold time
THD:DAT
0
鈥�
ns
Data input setup time
TSU:DAT
250
100
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
STOP condition setup time
TSU:STO
4000
600
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
Output valid from clock
TAA
鈥�
3500
900
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
Bus free time: Time the bus must
be free before a new transmis-
sion can start
TBUF
4700
1300
鈥�
ns
4.5V
鈮� Vcc 鈮� 5.5V (E Temp range)
3.0V
鈮� Vcc 鈮� 4.5V
4.5V
鈮� Vcc 鈮� 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
20+0.1
CB
250
ns
(Note 1), CB
鈮� 100 pF
Input filter spike suppression
(SDA and SCL pins)
TSP
鈥�
50
ns
Write cycle time
TWC
鈥�4
ms
Endurance
1M
鈥�
cycles
25
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL and avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on Microchip鈥檚 website.
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