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| 型號： | PIC12C671-04I/SM |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 79/129頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 1KX14 A/D 8-SOIJ |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 90 |
| 系列： | PIC® 12C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 4x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.209"，5.30mm 寬） |
| 包裝： | 管件 |
| 配用： | AC164312-ND - MODULE SKT FOR PM3 16SOIC ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1048-ND - ADAPTER 8-SOIC TO 8-DIP 309-1047-ND - ADAPTER 8-SOIC TO 8-DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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1999 Microchip Technology Inc.
DS30561B-page 53
PIC12C67X
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC12C67X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
Oscillator selection
Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID locations
In-circuit serial programming
The PIC12C67X has a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The INTRC/EXTRC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
9.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h-
3FFFh),
which
can
be
accessed
only
during
programming.
REGISTER 9-1:
CONFIGURATION WORD
CP1
CP0
CP1
CP0
CP1
CP0 MCLRE
CP1
CP0
PWRTE WDTE FOSC2 FOSC1 FOSC0
Register:
CONFIG
Address
2007h
bit13
bit0
bit 13-8, CP<1:0>: Code Protection bit pairs(1)
6-5:
11
= Code protection off
10
= Locations 400h through 7FEh code protected (do not use for PIC12C671 and PIC12CE673)
01
= Locations 200h through 7FEh code protected
00
= All memory is code protected
bit 7:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear Enabled
0 = Master Clear Disabled
bit 4:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC<2:0>: Oscillator Selection bits
111
= EXTRC, Clockout on OSC2
110
= EXTRC, OSC2 is I/O
101
= INTRC, Clockout on OSC2
100
= INTRC, OSC2 is I/O
011
= Invalid Selection
010
= HS Oscillator
001
= XT Oscillator
000
= LP Oscillator
Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
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