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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC12C671-04/SM |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 36/129闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 1KX14 A/D 8-SOIJ |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | PIC® 12C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 4MHz |
| 澶栧湇瑷�(sh猫)鍌欙細 | POR锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 5 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 1.75KB锛�1K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 128 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 3 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 4x8b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 8-SOIC锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 绠′欢 |
| 閰嶇敤锛� | AC164312-ND - MODULE SKT FOR PM3 16SOIC ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 309-1048-ND - ADAPTER 8-SOIC TO 8-DIP 309-1047-ND - ADAPTER 8-SOIC TO 8-DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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PIC12C67X
DS30561B-page 14
1999 Microchip Technology Inc.
Bank 1
80h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(1)
PCL
Program Counter鈥檚 (PC) Least Significant Byte
0000 0000
83h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
84h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRIS
鈥�
GPIO Data Direction Register
--11 1111
86h
鈥�
Unimplemented
鈥�
87h
鈥�
Unimplemented
鈥�
88h
鈥�
Unimplemented
鈥�
89h
鈥�
Unimplemented
鈥�
8Ah(1,2)
PCLATH
鈥�
Write Buffer for the upper 5 bits of the PC
---0 0000
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000u
8Ch
PIE1
鈥擜DIE
鈥�
-0-- ----
8Dh
鈥�
Unimplemented
鈥�
8Eh
PCON
鈥�
鈥擯OR
鈥�
---- --0-
---- --u-
8Fh
OSCCAL
CAL3
CAL2
CAL1
CAL0
CALFST
CALSLW
鈥�
0111 00--
uuuu uu--
90h
鈥�
Unimplemented
鈥�
91h
鈥�
Unimplemented
鈥�
92h
鈥�
Unimplemented
鈥�
93h
鈥�
Unimplemented
鈥�
94h
鈥�
Unimplemented
鈥�
95h
鈥�
Unimplemented
鈥�
96h
鈥�
Unimplemented
鈥�
97h
鈥�
Unimplemented
鈥�
98h
鈥�
Unimplemented
鈥�
99h
鈥�
Unimplemented
鈥�
9Ah
鈥�
Unimplemented
鈥�
9Bh
鈥�
Unimplemented
鈥�
9Ch
鈥�
Unimplemented
鈥�
9Dh
鈥�
Unimplemented
鈥�
9Eh
鈥�
Unimplemented
鈥�
9Fh
ADCON1
鈥�
PCFG2
PCFG1
PCFG0
---- -000
TABLE 4-1:
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as 鈥�0鈥�.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as 鈥�0鈥�.
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