參數(shù)資料
型號(hào)： PIC10F220
廠商： Microchip Technology Inc.
英文描述： 6-Pin, 8-Bit Flash Microcontrollers
中文描述： 6引腳，8位閃存微控制器
文件頁(yè)數(shù)： 37/78頁(yè)
文件大?。?/td> 583K
代理商： PIC10F220
2006 Microchip Technology Inc.
Preliminary
DS41270B-page 35
PIC10F220/222
TABLE 8-2:
RESET CONDITION FOR SPECIAL REGISTERS
8.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘
1
’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
DD
and the pin is assigned to be a I/O. See Figure 8-1.
FIGURE 8-1:
MCLR SELECT
8.4
Power-on Reset (POR)
The PIC10F220/222 devices incorporate an on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
V
DD
has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the GP3/MCLR/V
PP
pin as MCLR and tie through a
resistor to V
DD
, or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor
(refer to Table 10-2 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset. A maximum rise time for
V
DD
is specified. See
Section 10.0 “Electrical Char-
acteristics”
for details.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-2.
The Power-on Reset circuit and the Device Reset
Timer (see
Section 8.5 “Device Reset Timer (DRT)”
)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 1.125 ms, it will reset
the Reset latch and thus end the on-chip Reset signal.
A power-up example where MCLR is held low is shown
in Figure 8-3. V
DD
is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset T
DRT
msec after MCLR goes high.
In Figure 8-4, the on-chip Power-on Reset feature is
being used (MCLR and V
DD
are tied together or the pin
is programmed to be GP3). The V
DD
is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-5 depicts a
problem situation where V
DD
rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and V
DD
actually reach their full value, is
too long. In this situation, when the start-up timer times
out, V
DD
has not reached the V
DD
(min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-4).
For additional information, refer to Application Notes
AN522,
“Power-Up Considerations”
(DS00522) and
AN607,
“Power-up Trouble Shooting”
(DS00607).
STATUS Addr: 03h
PCL Addr: 02h
Power-on Reset
0--1 1xxx
1111 1111
MCLR Reset during normal operation
0--u uuuu
1111 1111
MCLR Reset during Sleep
0--1 0uuu
1111 1111
WDT Reset during Sleep
0--0 0uuu
1111 1111
WDT Reset normal operation
0--0 uuuu
1111 1111
Wake-up from Sleep on pin change
1--1 0uuu
1111 1111
Legend:
u
= unchanged,
x
= unknown, – = unimplemented bit, read as ‘
0
’.
GP3/MCLR/V
PP
MCLRE
Internal MCLR
GPWU
Weak Pull-up
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in Reset until the
operating conditions are met.
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