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| 型號(hào)： | PIC10F204-I/MC |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 20/94頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 256X12 8DFN |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 150 |
| 系列： | PIC® 10F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 3 |
| 程序存儲(chǔ)器容量： | 384B（256 x 12） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 16 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VFDFN 裸露焊盤 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 637 (CN2011-ZH PDF) |
| 配用： | AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN AC103003-ND - BOARD DEMO PIC10F CAP TOUCH AC163020-2-ND - ADAPTER PROGRAM PIC10F 2X3 DFN |
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2007 Microchip Technology Inc.
DS41239D-page 25
PIC10F200/202/204/206
5.0
I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimple-
mented and read as ‘0’s. Please note that GP3 is an
input-only pin. Pins GP0, GP1 and GP3 can be config-
ured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not pin selectable. If GP3/MCLR is config-
ured as MCLR, weak pull-up is always on and wake-up
on change for this pin is not enabled.
5.2
TRIS Registers
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are GP3, which is input-only and the GP2/T0CKI/
COUT/FOSC4 pin, which may be controlled by various
registers. See Table 5-1.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
TABLE 5-1:
ORDER OF PRECEDENCE
FOR PIN FUNCTIONS
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3 which is input-
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
FIGURE 5-1:
PIC10F200/202/204/206
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
Priority
GP0
GP1
GP2
GP3
1
CIN+
CIN-
FOSC4
I/MCLR
2
TRIS GPIO
COUT
—
3
—
—T0CKI
—
4
—
—TRIS GPIO
—
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
P
N
WR
Port
TRIS
‘f’
Data
TRIS
RD Port
VSS
VDD
I/O
pin
W
Reg
Latch
Reset
Note 1: See Table 3-2 for buffer type.
VSS
VDD
(1)
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