86
AT89/83EB5114
4311C–8051–02/08
Notes: 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 42.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; Vpp = RST = VCC. ICC would be slightly higher if a crystal oscillator used
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC -
0.5 V; XTAL2 N.C; Vpp = RST = VSS (see Figure 40.). 3. Power Down ICC is measured with all output pins disconnected; Vpp = VSS; XTAL2 NC.; RST = Vcc (see Figure 41.). 4. Not Applicable
5. Typical are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
3.3V.
6. If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. When port configuration have weak pull-up activated.
9. When port configuration is quasi-bidirectional.
10. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 42.), VIL = VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; RST= VCC;. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
Figure 38. ICC Test Condition, under reset
Figure 39. Operating ICC Test Condition
tR
Supply rise time
1us
1s
Table 1. DC Parameters for Low Voltage (Continued)
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
VCC
ICC
(NC)
C L O C K
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
ICC
(NC)
C L O C K
SIGNAL
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
VCC