參數(shù)資料
型號(hào): PI90LVT386AE
廠商: Pericom
文件頁(yè)數(shù): 1/8頁(yè)
文件大?。?/td> 0K
描述: IC 16 DIFF LINE RCVR 3ST 64TSSOP
標(biāo)準(zhǔn)包裝: 28
類型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 0/16
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 64-TFSOP (0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 64-TSSOP
包裝: 管件
1
PS8574D
11/11/08
Block Diagram
Features
Sixteen line receivers meet or exceed the requirements of the
ANSI TIA/EIA-644-1995 Standard
Designed for signaling rates up to 660 Mbps
0V to 3V common-mode input voltage range
Operates from a single 3.3V supply
Typical propagation delay time: 2.6ns
Output skew 100ps (typical)
Part-to-part skew is less than 1ns
Integrated 110-Ohm termination on PI90LVT386
Low Voltage TTL (LVTTL) levels are 5V tolerant
Open-circuit fail safe
Flow-through pin out
Packaging (Pb-free & Green available):
- 64-Pin Thin Shrink Small Output TSSOP (A)
Description
ThePI90LVx386familyconsistsof sixteendifferentiallinereceivers
with 3-state outputs that implement Low-Voltage Differential
Signaling (LVDS). Any of the differential receivers will provide a
valid logical output state with a ±100mV differential input voltage
within the input common-mode voltage range that allows 0 to 3V of
ground potential difference between two LVDS nodes. The indepen-
dent EN pins can be used to place the outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In high-
impedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-ohms with a
100-Ohmterminationresistor.ThePI90LVT386integratesthetermi-
nating resistors while the PI90LV386 requires external resistors.
The transmission media may be printed circuit board traces,
backplanes, or cables. The PI90LV386’s 16 receivers integrated into
the same substrate allow precise timing alignment.
These parts are characterized for operation from –40°C to 85°C.
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PI90LV386/PI90LVT386
High-Speed Differential Line Receivers
1
1RIN1+
1RIN1–
1RIN2+
1RIN2–
1RIN3+
1RIN3–
1RIN4–
2RIN1+
2RIN1–
2RIN2–
2RIN3+
2RIN3–
2RIN4+
2RIN4–
1RIN4+
2RIN2–
3RIN1+
3RIN4–
3RIN1–
3RIN2+
3RIN2–
3RIN3+
3RIN3–
EN3
GND
VCC
GND
1ROUT4
EN2
1ROUT1
VCC
1ROUT2
1ROUT3
2ROUT4
2ROUT1
2ROUT2
2ROUT3
3ROUT4
3ROUT1
3ROUT2
3ROUT3
4ROUT4
4ROUT1
4ROUT2
4ROUT3
GND
VCC
EN1
VCC
GND
EN4
GND
16 Receivers
3RIN4+
4RIN1+
4RIN1–
4RIN2+
4RIN2–
4RIN3+
4RIN3–
4RIN4+
4RIN4–
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PinConfiguration
64-Pin
A
08-0295
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