參數(shù)資料
型號(hào): PI90LVT211QE
廠商: Pericom Semiconductor Corp.
英文描述: 1:6 Differential Clock Distribution Chip
中文描述: 1:6差分時(shí)鐘分配芯片
文件頁(yè)數(shù): 3/9頁(yè)
文件大小: 185K
代理商: PI90LVT211QE
3
PS8535C 10/04/04
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PI90LV211/PI90LVT211
1:6 Differential Clock
Distribution Chip
Notes:
1. Within-Device skew is defined for identical transitions on similar paths through a device.
2. Setup, Hold, and Disable times are all relative to a falling edge on CLK or SCLK.
3. Minimum input swing for which AC parameters are guaranteed. Full DC LVDS output swings will be generated with only 50mV input
swings.
4. The range in which the high level of the input swing must fall while meeting the V
PP
spec.
5. t
SKIR
is the difference in receiver propagation delay (t
PLH
-t
PHL
) of one device, and is the duty cycle distortion of the output at any given
temperature and V
CC
. The propagation delay specification is a device-to-device worst case over process, voltage, and temperature.
6. t
SK2R
is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction. This
parameter is guaranteed by design and characterization.
7. Generator input conditions: t
r
t
f
< 1ns, 50% duty cycle, differential (1.10V to 1.35V peak-peak).
Output Criteria: 60%/40% duty cycle, V
OL
(max) 0-4V, V
OH
(min) 2.7V, Load - 7pF (stray plus probes).
8. C
L
includes probe and fixture capacitance.
9. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Z
O
= 50 ohms, t
r
= 1ns, t
f
= 1ns (35%-65%). To ensure fastest propagation
delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
Switching Characteristics over Recommended Operating Conditions
(unless otherwise noted)
(8,9)
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