參數資料
| 型號： | PI90LVB16L |
| 廠商： | Pericom |
| 文件頁數： | 9/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 1:6 24-TSSOP |
| 產品變化通告： | Product Discontinuation Notice 29/May/2007 |
| 標準包裝： | 62 |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/無 |
| 輸入： | BLVDS |
| 輸出： | CMOS，LVTTL |
| 頻率 - 最大： | 160MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
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6
PS8536C
11/11/08
PI90LVB16
3V Bus LVDS 1-to-6
Clock Buffer/Bus Transceiver
Switching Characteristics
Differential Driver Timing Requuirements
(Over supply voltage and operating temperature ranges, unless otherwise specificed(7,8)
Notes:
1. “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. These ratings
are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of
device operation.
2. ESD Rating: ESD qualification is performed per the following: HBM (1.5k
Ω, 100pF), Machine Model (250V, 0Ω), IEC 1000-4-2. All VCC
pins connected together, all ground pins connected together.
3. Current into device pins are defined as positive. Current out of device pins defined as negative. All voltages are referenced to ground except
VID, VOD, VTH, and VTL
4. All typicals are given for: VCC = +3.3V and TA = +25°C.
5. The VCMR range is reduced for larger VID. Example: If VID=400 mV, then VCMR is 2V to 2.2VAVID up to
VCC-0V may be applied
between the CLKI/O+ and CLKI/O– inputs, with the Common Mode set to VCC/2.
6. Only one output should be momentarily shorted at a time. Do not exceed package power dissipation rating.
7. CL includes probe and fixture capacitance.
8. Generator waveform for all tests unless otherwise specified: f = 25 MHz, Zo = 50
Ω, tr = 1ns, tf = 1ns (10%–90%). To ensure fastest
propagation delay and minimum skew, clock input edge rates should not be slower than 1ns/V; control signals not slower than 3ns/V.
In general, the faster the input edge rate, the better the AC performance,
9. All device output transition times are based on characterization measurements and are guaranteed by design.
10. tSKIR is the difference in receiver propagation delay
tPLH-tPHL of one device, and is the duty cycle distortion of the output at any given
temperature and VCC. The propagation delay specification is a device-to-device worst case over process, voltage and temperature.
11. tSK2R is the difference in receiver propagation delay between channels in the same device of any outputs switching in the same direction.
This parameter is guaranteed by design and characterization.
12. tSK3R part-to-part skew, is the difference in receiver propagation delay between devices of any outputs switching in the same direction.
This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK3R is
defined as Max-Min differential propagation delay. This parameter is guaranteed by design and characterization.
13. tSK1D is the difference in driver propagation delay
tPLH-tPHLand is the duty cycle distortion of the CLKI/O outputs.
14. tSK2D part-to-part skew, is the difference in driver propagation delay between devices of any outputs switching in the same direction. This
specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSK2D is
defined as Max-Min differential propagation delay.
15. Generator input conditions: trtf < 1ns, 50% duty cycle, differential (1.10V to 1.35V pk-pk). Output Criteria: 60%/40% duty cycle,
VOL(max) 0.4V, VOH(min) 2.7V, Load - 7pF (stray plus probes).
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