參數(shù)資料
型號(hào): PI90LV031ALE
廠商: Pericom
文件頁(yè)數(shù): 10/11頁(yè)
文件大?。?/td> 0K
描述: IC LVDS LINE DVR QUAD 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
類(lèi)型: 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù): 4/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
8
DS657F3
CS4265
VA
17 Analog Power (Input) - Positive power for the internal analog section.
AGND
18 Analog Ground (Input) - Ground reference for the internal analog section.
AOUTA
AOUTB
19, 20 Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Characteris-
tics specification table.
MUTEC
21 Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master
clock left/right clock frequency ratio is incorrect, or power-down.
VLS
22 Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio inter-
face. Refer to the Recommended Operating Conditions for appropriate voltages.
TXSDIN
23 Transmitter Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
SDIN2
24 Serial Audio Data Input 2 (Input) - Input for two’s complement serial audio data.
SDIN1
25 Serial Audio Data Input 1 (Input) - Input for two’s complement serial audio data.
SDOUT
26 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.
SCLK
27 Serial Clock (Input/Output) - Serial clock for the serial audio interface.
LRCK
28 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the
serial audio data line.
MCLK
29 Master Clock (Input) - Clock source for the delta-sigma modulators.
DGND
30 Digital Ground (Input) - Ground reference for the internal digital section.
VD
31 Digital Power (Input) - Positive power for the internal digital section.
TXOUT
32 Transmitter Line Driver Output (Output) - IEC60958-3 driver output.
Thermal Pad
-
Thermal Pad
- Thermal relief pad for optimized heat dissipation.
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