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參數(shù)資料
| 型號(hào)： | PI7C8154-33 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 76/115頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8154-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 76 of 115
July 31, 2003 – Revision 1.031
10.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
To enable live insertion mode, the live insertion mode bit in the chip control register must
be set to 1, and the output enable control for GPIO[3] must be set to input only in the GPIO
output enable control register. When live insertion mode is enabled, whenever GPIO[3] is
driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are
internally masked to 0. This means that, as a target, PI7C8150B no longer accepts any I/O
or memory transactions, on either interface. When read, the register bits still reflect the
value originally written by a configuration write command; when GPIO[3] is deasserted,
the internal enable bits return to their original value (as they appear when read from the
command register). When this mode is enabled, as a master, PI7C8150B completes any
posted write or delayed request transactions that have already been queued.
Delayed completion transactions are not returned to the master in this mode because
PI7C8150B is not responding to any I/O or memory transactions during this time.
PI7C8150B continues to accept configuration transactions in live insertion mode. Once live
insertion mode brings PI7C8150B to a halt and queued transactions are completed, the
secondary reset bit in the bridge control register can be used to assert S_RST_L, if desired,
to reset and tri-state secondary bus devices, and to enable any live insertion hardware.
11
PCI POWER MANAGEMENT
PI7C8150B
incorporates functionality that meets the requirements of the
PCI Power
Management Specificatio
n,
Revision 1.
0. These features include:
!
PCI Power Management registers using the Enhanced Capabilities Port (ECP) address
mechanism
!
!
Support for D0, D3
hot
and D3
cold
power management states
Support for D0, D1, D2, D3
hot
, and D3
cold
power management states for devices
behind the bridge
!
Support of the B2 secondary bus power state when in the D3
hot
power management
state
Table 11-1
shows the states and related actions that PI7C8150B performs during power
management transitions. (No other transactions are permitted.)
Table 11-1. Power Management Transitions
Current Status
D0
Next State
D3cold
Action
Power has been removed from PI7C8150B. A power-up reset must
be performed to bring PI7C8150B to D0.
If enabled to do so by the BPCCE pin, PI7C8150B will disable the
secondary clocks and drive them LOW.
Unimplemented power state. PI7C8150B will ignore the write to the
power state bits (power state remains at D0).
Unimplemented power state. PI7C8150B will ignore the write to the
power state bits (power state remains at D0).
D0
D3hot
D0
D2
D0
D1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154ANA | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64-Bit/66MHz 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
| PI7C8154BNA | 制造商:Pericom Semiconductor Corporation 功能描述: |
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