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參數(shù)資料
| 型號(hào)： | PI7C8152B |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁(yè)數(shù)： | 14/115頁(yè) |
| 文件大小： | 879K |
| 代理商： | PI7C8152B |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 14 of 115
July 31, 2003 – Revision 1.031
Name
P_M66EN
Pin #
102
Pin #
R14
Type
I
Description
Primary Interface 66MHz Operation.
This input is used to specify if PI7C8150B is capable of
running at 66MHz. For 66MHz operation on the Primary
bus, this signal should be pulled “HIGH”. For 33MHz
operation on the Primary bus, this signal should be
pulled LOW. In synchronous mode, S_M66EN will be
driven LOW, forcing the secondary bus to run at 33MHz
also. Also, bit [21] offset 04h is determined by CFG66.
If P_M66EN is LOW, S_M66EN will not be driven
LOW (please see S_M66EN pin description).
In asynchronous mode, the logic value of P_M66EN is
used to generate the value of bit[21] offset 04h.
SECONDARY BUS INTERFACE SIGNALS
2.2.2
Name
S_AD[31:0]
Pin #
206, 204, 203,
201, 200, 198,
197, 195, 192,
191, 189, 188,
186, 185, 183,
182, 165, 164,
162, 161, 159,
154, 152, 150,
147, 146, 144,
143, 141, 140,
138, 137
194, 180, 167, 149
Pin #
A4, D5, C5,
A5, B5, D6,
A6, C6, C7,
A7, B7, C8,
A8, B8, A9,
C9, C12, D12,
A14, B13, A15,
B16, E13, C16,
E14, D16, F13,
E16, F14, F15,
F16, G16
B6, B9, B12,
E15
Type
TS
Description
Secondary Address/Data:
Multiplexed address and
data bus. Address is indicated by S_FRAME_L
assertion. Write data is stable and valid when
S_IRDY_L is asserted and read data is stable and valid
when S_IRDY_L is asserted. Data is transferred on
rising clock edges when both S_IRDY_L and
S_TRDY_L are asserted. During bus idle, PI7C8150B
drives S_AD to a valid logic level when S_GNT_L is
asserted respectively.
S_CBE[3:0]
TS
Secondary Command/Byte Enables:
Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C8150B drives
S_CBE[3:0] to a valid logic level when the internal
grant is asserted.
Secondary Parity:
Parity is even across S_AD[31:0],
S_CBE[3:0], and S_PAR (i.e. an even number of 1’s).
S_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
S_FRAME_L) for address parity. For write data phases,
S_PAR is an input and is valid one clock after
S_IRDY_L is asserted. For read data phase, S_PAR is
an output and is valid one clock after S_TRDY_L is
asserted. Signal S_PAR is tri-stated one cycle after the
S_AD lines are tri-stated. During bus idle, PI7C8150B
drives S_PAR to a valid logic level when the internal
grant is asserted.
Secondary FRAME (Active LOW):
Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of S_FRAME_L
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted state
for one cycle.
Secondary IRDY (Active LOW):
Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted until
the end of the data phase. Before tri-stated, it is driven
to a de-asserted state for one cycle.
Secondary TRDY (Active LOW):
Driven by the target
of a transaction to indicate its ability to complete current
data phase on the secondary side. Once asserted in a
data phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
S_PAR
168
A13
TS
S_FRAME_L
179
A10
STS
S_IRDY_L
177
B10
STS
S_TRDY_L
176
C10
STS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8154-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8152BEVB | 功能描述:界面開(kāi)發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8152BMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 160-Pin MQFP |
| PI7C8152BMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8152BMAIE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI to PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
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