參數(shù)資料
型號: PI7C7300A
廠商: Pericom Semiconductor Corp.
英文描述: 3-PORT PCI-to-PCI BRIDGE
中文描述: 3端口PCI至PCI橋
文件頁數(shù): 58/109頁
文件大?。?/td> 779K
代理商: PI7C7300A
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 58 OF 109
09/25/03 Revision 1.09
Table 7-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
!
The PI7C7300A must be a master on the secondary bus.
!
The parity error response bit must be set in the bridge control register of secondary
interface.
!
The S_PERR# signal is detected asserted or a parity error is detected on the
secondary bus.
BIT
Table 7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED
Secondary
Detected Parity
Detected Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
0
1
0
0
0
1
0
0
0
1
0
0
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
X= don’t care
Table 7-5 shows assertion of P_PERR#. This signal is set under the following conditions:
!
PI7C7300A is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
!
The parity-error-response bit must be set in the command register of primary
interface.
!
PI7C7300A detects a data parity error on the primary bus or detects S_PERR#
asserted during the completion phase of a downstream delayed write transaction on
the target (secondary) bus.
Table 7-5 ASSERTION OF P_PERR#
P_PERR#
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
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