
PI7C7300A
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 69 OF 109
09/25/03 Revision 1.09
duration of S1_RESET# (S2_RESET#) assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers
at the time of secondary reset are discarded.
When S1_RESET# or S2_RESET# is asserted by means of the secondary reset bit,
PI7C7300A remains accessible during secondary interface reset and continues to respond
to accesses to its configuration space from the primary interface.
13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1
PRIMARY INTERFACE
P_CBE [3:0] #
0000
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
Action
Ignore
0001
0010
Do not claim. Ignore.
1.
If address is within pass through I/O range, claim and
pass through.
2.
Otherwise, do not pass through and do not claim for
internal access.
Same as I/O Read.
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1.
If address is within pass through memory range, claim
and pass through.
2.
If address is within pass through memory mapped I/O
range, claim and pass through.
3.
Otherwise, do not pass through and do not claim for
internal access.
Same as Memory Read.
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I.
Type 0 Configuration Read:
If the bridge’s IDSEL line is asserted, perform function
decode and claim if target function is implemented.
Otherwise, ignore. If claimed, permit access to target
function’s configuration registers. Do not pass through
under any circumstances.
II.
Type 1 Configuration Read:
1.
If the target bus is the bridge’s secondary bus: claim
and pass through as a Type 0 Configuration Read.
2.
If the target bus is a subordinate bus that exists behind
the bridge (but not equal to the secondary bus): claim
and pass through as a Type 1 Configuration Read.
3.
Otherwise, ignore.
I.
Type 0 Configuration Write: same as Configuration
Read.
II.
Type 1 Configuration Write (not special cycle
request):
1.
If the target bus is the bridge’s secondary bus: claim
and pass through as a Type 0 Configuration Write
2.
If the target bus is a subordinate bus that exists behind
the bridge (but not equal to the secondary bus): claim
and pass through unchanged as a Type 1 Configuration
Write.
3.
Otherwise, ignore.
III.
Configuration Write as Special Cycle Request
0011
0100
0101
0110
I/O Write
Reserved
Reserved
Memory Read
0111
1000
1001
1010
Memory Write
Reserved
Reserved
Configuration Read
1011
Configuration Write