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參數(shù)資料
| 型號(hào)： | PI74SSTVF32852ANBE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC REGSTRD BUFF 24B-28B 114LFBGA |
| 標(biāo)準(zhǔn)包裝： | 240 |
| 系列： | 74SSTVF |
| 邏輯類型： | 24 位至 48 位寄存緩沖器，非反相 |
| 元件數(shù)： | 1 |
| 每個(gè)元件的位元數(shù)： | 24 |
| 輸出電流高，低： | 8mA，8mA |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 114-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 114-LFBGA（16x5.5） |
| 包裝： | 托盤 |
1
PS8682A
11/10/08
Product Description
Pericom Semiconductor’s PI74SSTVF32852A logic circuit is
produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
All inputs are compatible with the JEDEC standard for SSTL_2,
except the LVCMOS reset (RESET) input. All outputs are SSTL_2,
Class II compatible.
The device operates from a differential clock (CK and CK). Data
registered at the crossing of CK going HIGH, and CK going LOW.
The PI74SSTVF32852A supports low-power standby operation.
When RESET is LOW, the differential input receivers are disabled,
and undriven (floating) data, clock and reference voltage (VREF)
inputs are allowed. In addition, when RESET is LOW, all registers
are reset, and all outputs are forced LOW. The LVCMOS RESET
input must always be held at a valid logic HIGH or LOW level.
To ensure defined outputs from the register before a stable clock
has been supplied, RESET must be held in the LOW state during
power up.
In the DDR DIMM application, RESET is specified to be completely
asynchronous with respect to CK and CK. Therefore, no timing
relationship can be guaranteed between the two. When entering
RESET, the register will be cleared and the outputs will be driven
LOW quickly, relative to the time to disable the differential input
receivers, thus ensuring no glitches on the output. However, when
comingoutof RESET,theregisterwillbecomeactivequickly,relative
to the time to enable the differential input receivers. When the data
inputs are LOW, and the clock is stable, during the time from the
LOW-to-HIGH transition of RESET until the input receivers
are fully enabled, the design must ensure that the outputs will
remainLOW.
Pericom’s PI74SSTVF32852A is characterized for operation from
0° to 70°C.
Product Features
PI74 SSTVF32852A is designed for low-voltage operation,
2.5VforPC1600~PC2700;2.6VforPC3200
Supports SSTL_2 Class I specifications on outputs
All Inputs are SSTL_2 Compatible, except RESET
whichisLVCMOS.
Designed for DDR Memory
Packaging:114-BallLFBGA
Pb-free available
Logic Block Diagram
Product Pin Description
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PI74SSTVF32852A
24-Bit to 48-Bit Registered Buffer
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Notes:
1. H = High Signal Level; L = Low Signal Level;
↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW
X = Irrelevant or floating
2. Output level before the indicated steady state input conditions were established.
08-0291
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI74SSTVF32852ANBEX | 功能描述:寄存器 24B to 48B Registered RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| PI74SSTVF32852NBEX | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 24-CH CMOS 114-Pin LFBGA T/R 制造商:Pericom Semiconductor Corporation 功能描述:IC, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA114 |
| PI74SSTVF32852NBX | 制造商:Pericom Semiconductor Corporation 功能描述:REGISTERED BFFR SGL 24-CH CMOS 114LFBGA - Tape and Reel |
| PI74ST1G04CX | 制造商:Pericom Semiconductor Corporation 功能描述:Inverter 1-Element CMOS 5-Pin SC-70 T/R |
| PI74ST1G08CEX | 功能描述:邏輯門 2 Input and Gate RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
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