參數(shù)資料
型號(hào)： PI74ALVCH16823
廠商： Pericom Semiconductor Corp.
英文描述： 18-Bit Bus-Interface Flip-Flop with 3-State Outputs
中文描述： 18位總線接口觸發(fā)器觸發(fā)器3態(tài)輸出
文件頁(yè)數(shù)： 1/5頁(yè)
文件大?。?/td> 327K
代理商： PI74ALVCH16823
1
PS8103 04/03/97
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PI74ALVCH16823
18-Bit Bus-Interface Flip-Flop
with 3-State Outputs
Logic Block Diagram
Product Description
Pericom Semiconductors PI74ALVCH series of logic circuits are
produced in the Companys advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The 18-bit PI74ALVCH16823 bus-interface flip-flop is designed
for 2.3V to 3.6V V
CC
operation. It features 3-state outputs designed
specifically for driving highly capacitive or relatively low-
impedance loads. This device is particularly suitable for
implementing wider buffer registers, I/O ports, bidirectional bus
drivers with parity, and working registers.
The PI74ALVCH16823 can be used as two 9-bit flip-flops or one
18-bit flip-flop. With the Clock Enable (CLKEN) input LOW, the
D-type flip-flops enter data on the low-to-high transitions of the
clock. Taking CLKEN HIGH disables the clock buffer, thus
latching the outputs. Taking the Clear (CLR) input LOW causes the
Q outputs to go LOW independently of the clock.
A buffered Output Enable (OE) input can be used to place the nine
outputs in either a normal logic state (high or low logic levels) or
high-impedance state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The high-impedance
state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
The Output Enable (OE) input does not affect the internal operation
of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Product Features
PI74ALVCH16823 is designed for low voltage operation
V
CC
= 2.3V to 3.6V
Hysteresis on all inputs
Typical V
OLP
(Output Ground Bounce)
< 0.8V at V
CC
= 3.3V, T
A
= 25°C
Typical V
OHV
(Output V
OH
Undershoot)
< 2.0V at V
CC
= 3.3V, T
A
= 25°C
Bus Hold retains last active bus state during 3-STATE,
eliminating the need for external pullup resistors
Industrial operation at 40°C to +85°C
Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI74ALVCH16823A 功能描述:IC 18-BIT INTERFACE-F/F 56-TSSOP RoHS:否 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:74ALVCH 產(chǎn)品變化通告:Product Discontinuation 27/Jan/2012 標(biāo)準(zhǔn)包裝:2,000 系列:74LCX 功能:標(biāo)準(zhǔn) 類型:D 型總線 輸出類型:三態(tài)非反相 元件數(shù):1 每個(gè)元件的位元數(shù):8 頻率 - 時(shí)鐘:150MHz 延遲時(shí)間 - 傳輸:1.5ns 觸發(fā)器類型:正邊沿 輸出電流高，低:24mA，24mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.209"，5.30mm 寬） 包裝:帶卷 (TR) 其它名稱:MC74LCX574MELG-NDMC74LCX574MELGOSTR
PI74ALVCH16823V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:18-Bit D-Type Flip-Flop
PI74ALVCH16825 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic | 18-Bit Buffer/Line Driver
PI74ALVCH16825A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit Buffer/Driver
PI74ALVCH16825V 制造商:未知廠家 制造商全稱:未知廠家 功能描述:9-Bit Buffer/Driver
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