Switching characteristics over recomme" />
參數(shù)資料
型號: PI6CU877NFE
廠商: Pericom
文件頁數(shù): 10/12頁
文件大?。?/td> 0K
描述: IC PLL CLOCK DRIVER DDR2 52VFBGA
產(chǎn)品變化通告: Product Discontinuation 03/Oct/2011
標(biāo)準(zhǔn)包裝: 364
類型: 時鐘緩沖器/驅(qū)動器,多路復(fù)用器
PLL:
主要目的: 存儲器,DDR2,SDRAM DIMM
輸入: SSTL-18
輸出: SSTL-18
電路數(shù): 1
比率 - 輸入:輸出: 1:10
差分 - 輸入:輸出: 是/是
頻率 - 最大: 270MHz
電源電壓: 1.7 V ~ 1.9 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 52-VFBGA
供應(yīng)商設(shè)備封裝: 52-VFBGA(4.5x7)
包裝: 托盤
7
PS8689G
01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
AC Specifications
Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)(15)
Parameter
Description
Diagram
AVDD, VDDQ = 1.8 ±0.1V
Units
Min.
Nom.
Max.
ten
OE to and Y/Y
see Fig 11
8
ns
tdis
OE to and Y/Y
see Fig 11
8
tjit(cc+)
Cycle-to-cycle jitter
see Fig 4
0
40
ps
tjit(cc-)
0
-40
t()
Static phase offset (11)
see Fig 5
-50
50
t()dyn
Dynamic phase offset
see Fig 10
-50
50
tsk(o)
Output clock skew
see Fig 6
40
tjit(per)
Period jitter(12)
see Fig 7
-40
40
tjit(hper)
Half period jitter(12) 160 to 270 MHz
see Fig 8
-75
75
Half period jitter(12) 271 to 360 MHz
see Fig 8
-50
50
slr(i)
Input clock slew rate
see Fig 9
1
2.5
4
V/ns
Output enable (OE)
see Fig 9
0.5
slr(o)
Output clock slew rate (14, 16)
see Fig 1, 9
1.5
2.5
3
VOX
Outpu differential-pair cross voltage(13)
see Fig 2
(VDDQ/2)
-0.1
(VDDQ/2)
+0.1
V
The PLL on the PI6CUx877 is capable of meeting all the above test parameters while supporting SSC synthesirers
with the following parameters:
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency deviation
0.00
-0.50
%
PI6CUx877 PLL design should target the values below to minimize the SCC induced skew:
PLL Loop Bandwidth
2.0
MHz
Notes:
11. Static Phase Offset does not include Jitter
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
13. VOX specified at the DRAM clock input or the test load.
14. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these
nominal values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered
DDR2 DIMM application.
15. There are two terminations that are used with the above ac tests. The load/board in Figure 2 is used to measure the input and output differen-
tial-pair cross-voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables should be used.
16. The Output slew rate is determined from IBIS model load shown in Figure1. It is measured single-ended.
08-0298
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