參數(shù)資料
型號: PI6C3Q993-5QE
廠商: Pericom
文件頁數(shù): 8/10頁
文件大?。?/td> 0K
描述: IC PROG PLL CLOCK DRIVER 28-QSOP
產(chǎn)品變化通告: Product Discontinuation Notice 11/Feb/2008
標(biāo)準(zhǔn)包裝: 48
系列: SuperClock®
類型: PLL 時(shí)鐘驅(qū)動(dòng)器
PLL: 帶旁路
輸入: CMOS
輸出: CMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:8
差分 - 輸入:輸出: 無/無
頻率 - 最大: 85MHz
除法器/乘法器: 是/是
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 28-QSOP
包裝: 管件
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PI6C3Q991, PI6C3Q993
3.3V Programmable Skew PLL Clock Driver SuperClock
7
PS8449H
10/27/09
Table 9. Switching Characteristics Over Operating Range
Notes:
11.
All timing tolerances apply for FNOM
≥ 25MHz. Guaranteed by design and characterization.
12.
Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay
has been selected when all are loaded with the specified load.
13.
tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
14.
tSKEW0 is the skew between outputs when they are selected for 0tU.
15.
There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
16.
tDEV is output-to-output skew between any two devices operating under the same conditions (VCC , ambient temperature,
air flow, etc.)
17.
tLOCK is time required before synchronization is achieved. This specification is valid only after VCC is stable & within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is
within specified limits.
18.
tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
19.
Measured at 2.0V.
20.
Measured at 0.8V.
21.
Refer to Table10 for more detail.
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09-0003
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