參數(shù)資料
型號: PI6C3991JE
廠商: Pericom
文件頁數(shù): 7/11頁
文件大小: 0K
描述: IC PROG SKEW CLOCK DRIVER 32PLCC
產(chǎn)品變化通告: Product Discontinuation Notice 22/Jan/2010
標準包裝: 32
系列: SuperClock®
類型: 時鐘緩沖器
PLL:
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 5:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 80MHz
除法器/乘法器: 是/是
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LCC(J 形引線)
供應商設(shè)備封裝: 32-PLCC(11.43x13.97)
包裝: 管件
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PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
5
PS8450D
11/12/08
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Switching Characteristics PI6C3991 (Over the Operating Range)(2,7)
Notes:
7.
Test measurement levels for the PI6C3991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less
and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8.
Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9.
SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has
been selected when all are loaded with 30pF and terminated with 50 Ohm to VCC/2.
10. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
11. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
12. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns.
13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
14. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow,
etc.)
15. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4
specifications.
16. Specified with outputs loaded with 30pF for the PI6C3991 and PI6C3991-5 devices. Devices are terminated through 50 Ohm to VCC/
2. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
17. tORISE and tOFALL measured between 0.8V and 2.0V.
18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specifiedlimits.
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