參數(shù)資料
型號: PI6C3991J
廠商: Pericom
文件頁數(shù): 2/11頁
文件大小: 0K
描述: IC PROG SKEW CLOCK DRIVER 32PLCC
標(biāo)準(zhǔn)包裝: 32
系列: SuperClock®
類型: 時鐘緩沖器
PLL:
輸入: LVTTL
輸出: LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 5:4
差分 - 輸入:輸出: 無/無
頻率 - 最大: 80MHz
除法器/乘法器: 是/是
電源電壓: 2.97 V ~ 3.63 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 32-PLCC(11.43x13.97)
包裝: 管件
其它名稱: Q1006950
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10
PS8450D
11/12/08
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
Skew Clock Buffer - SuperClock
Figure 8. Board-to-Board Clock Distribution
Figure 8 shows the PI6C3991 connected in series to construct a zero
skew clock distribution tree between boards. Delays of the down
stream clock buffers can be programmed to compensate for the wire
length (i.e., select negative skew equal to the wire delay) necessary
to connect them to the master clock source, approximating a zero-
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
System
Clock
REF
LOAD
Z0
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
LOAD
Z0
LOAD
Z0
L1
L2
L3
L4
delay clock tree. Cascaded clock buffers will accumulate low-fre-
quency jitter because of the non-ideal filtering characteristics of the
PLL filter. It is recommended that not more than two clock buffers be
connected in series.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI6C3991JE 功能描述:鎖相環(huán) - PLL Programmable Skew Zero Delay RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
PI6C3991JI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver
PI6C3Q991 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Programmable Skew PLL Clock Driver
PI6C3Q991-2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Eight Distributed-Output Clock Driver
PI6C3Q991-2J 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3.3V Programmable Skew PLL Clock Driver